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Circuit
Description—
7S11
The
diodes,
CR272
and
CR274,
are reverse
biased
by
9
volts
each.
If
the
output
tries
to
go
more
positive
than
about
+10
volts,
CR274
conducts
(9
+
0.6
=
9.6
volts)
reducing the
amplifier gain to
much
less
than
1.
If
the
output
tries
to
go
more
negative
than
about
—10
volts,
CR272
conducts, reducing the
amplifier gain to
much
less
than
1.
The
clamping diodes
prevent the
amplifier
transis-
tors
from
saturating
at
the
time
of
an overdrive
signal,
and
thus ensure
fast
transition
away from
the
clamped
voltage
at
the next sample.
CR242
conducts only
when Q242
is
removed from
the
socket while the
power
is
on,
thus keeping
—50
volts off
the source
leads
when Q242
is
plugged
in.
Temperature
compensation
of the amplifier
is
accomplished
effectively
by
the source-coupled
FET
input
amplifier
and
CR257
and
CR259.
Q252
is
an
active
load
for
Q242.
This
active
load
causes the
signal
current
to
the base of
Q256
to
be about
twice the
signal
current
out
of
the drain of
Q242
right.
Q252
also serves
to
speed
up
the
circuit
response
time.
The
two
identical
halves of
Q242
compensate
each other
so
their
total
current
does not change with temperature
change.
CR257
and
CR259
have junction-drop temperature
coefficients similar to
Q262
and
Q266
base-emitter junc-
tions,
and
thus
stabilize
the
output
circuit.
The
Memory
amplifier drives the front panel
vertical
output
jack
through
a resistive
attenuator that
delivers
40%
of the
memory
signal
through 10
k^2.
The
jack
is
labeled
VERT
SIG
OUT,
0.2
V/DIV,
10
kSl.
The
memory
output
signal
is
the standard deflection
signal
mentioned
in
Section
3,
and
is
0.5
volt/CRT
division.
The
Memory
drives
the
Vertical
Output
through
the
Invert switch.
NOTE
The
Memory
output
limits
of
±10
volts
at
0.5 V/div
equals
40
CRT
divisions
of
display
area,
required
when
operating at high
sensitivity
and
many
divisions
of
DC
OFFSET.
The whole
pulse amplifier chain
is
designed
for
full
response
and
fast
recovery so
that
on-screen displays
have
accurate deflection
factors
and
DC
offset reference.
Such
operation provides
accurate
signals
at the front
pane! Vert
Output
jack,
even though
much
of
the
signal
is
not
displayed
on
the
CRT.
Output
Amplifier
The Output
Amplifier diagram
includes the Vertical
Out-
put and the
Real
Time
Trigger.
The
Vertical
Output
amplifier follows
the
Invert switch,
INVERT/+UP
which
sets
the
signal
path
from
the
Memory
circuit.
The
Vertical
Output
amplifier consists of
a
two-
stage push-pull
balanced
circuit.
The
first
stage
includes the
VARIABLE
gain control
and
the
Position
adjustment
in
the
common
emitter
circuit
of
0314
and
Q334.
The
Position
adjustment changes
the current
through each
side
of the
push-pull
circuit
for
a
center-screen
output
voltage.
Gain
of
the
stage
is
controlled
by
the
VARIABLE
control.
Maxi-
mum
gain
occurs with
minimum
resistance
between
the
two
emitters.
The
Variable
Balance adjustment
sets
the
level
on
the base of
Q334
so that
no
current flows
between
emitters
under
no-signal
conditions.
This ensures
that there
is
no
ground
reference
shift
of the trace
when
the
VARIABLE
control
is
turned.
The
second
stage of
the
Vertical
Output
amplifier
in-
cludes the
GAIN
adjustment,
which
varies
the emitter
de-
generation
of
Q344
and
Q354. The
push-pull
outputs
are
applied to the oscilloscope
vertical
amplifier
as
a
current
source.
The
Real
Time
Trigger amplifier
(Q362
and
Q366)
is
a
balanced
circuit
with
push-pull input
from
the
first
stage
of
the Vertical
Output
amplifier. Positive
and
negative
trigger
signals
are applied to
the timing unit
through
the
oscillo-
scope
interface.
Gate Generator
The
Gate Generator diagram
includes the Real
Time
Oscillator
and
Memory
Gate
Driver.
The
sampling
drive
pulse
from
the sampling
sweep
unit
is
slewed
in
time
from
the
initial
sweep
trigger
event
and
further
delayed
in
the
Delay
circuit.
The
Memory
Gate
Driver
circuit
provides the
proper
time-positioning of the
Memory
Gate
pulse
so that
the
error
signals are
gated
at
the correct time.
The
Real
Time
Oscillator
oscillates at
about
47.5
kHz
to
start
the
sampling process
when
driven
by
a
non-sampling
sweep
unit.
The
Memory
Gate
Driver
is
preceded
by
a
blocking
oscil-
lator
(0430
and
associated
components) which
standardizes
the
risetime
and amplitude
of the
sampling
pulse
from
the
sampling sweep.
Until
the
positive
sampling
drive pulse
occurs,
0430
is
cut
off
and
its
collector
is
at
+15
volts.
The
arriving
pulse causes the
transistor to
start
conduction
as a
normal
amplifier,
but
the regenerative
feedback
from
T430
via
CR430
quickly
drives
0430
into saturation.
As
the
cur-
rent
through
T430
reaches
a
steady
value,
the
counter-EMF
generated
in
the
secondary
of
T430
is
stopped by
the
reverse-biasing of
CR430.
0430
remains
in
saturation
until
cut
off
when
the
sampling
drive pulse ends.
The
Memory
Gate
Driver
circuit
consists of
a
low-
current amplifier
(0452) and
a
monostable
multivibrator
(0456-0464). At
quiescence, the base voltage
of
0452
(determined
by
the
DELAY
control
setting)
is
between
+1
1
and
+15
volts.
The
current
through
0542
is
about
1
mA,
which
is
insufficient to
forward-bias
0456. Diode
CR455
holds the base
of
0456
at
—15.6
volts to
ensure
that the
4-8
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