Table of Contents
Advertisement
KPXI System Controller User's Manual
high levels of environmental performance required by the vibration, shock, temperature, and
humidity extremes of industrial environments.
The Model KPXI-CON controller utilizes a 32-bit/33MHz PCI bus and can be used in the
Keithley Instruments PXI chassis listed below:
As PXI compliant controllers they can be used with any PXI compliant chassis from any
manufacturer.
CPU support
The KPXI-CON controller supports a single Intel
478-pin Micro-FCPGA or 479-ball Micro-FCBGA package. The standard Model KPXI-CON
controller comes with a CPU socket which can be installed with a Micro-FC-PGA package CPU,
including Pentium M 1.1GHz, 1.6GHz and 1.8GHz. The Pentium M processor runs at a core speed
up to 1.8GHz, with a Front Side Bus (FSB) speed of 400MHz.
The Intel Pentium M processor is a high performance, low power mobile processor with several
micro-architectural enhancements over existing Intel mobile processors. The key features of the
processor are listed as follows:
The Pentium M processor runs at a core speed up to 1.8GHz, with a Front Side Bus (FSB) speed
of 400MHz.
Memory support
The Model KPXI-CON controller is based on Intel 855GME chipset, which consists of 855GME
Graphics Memory Controller Hub (GMCH) and the 6300ESB I/O Controller Hub (ICH). The GMCH
system memory interface supports the following features:
KPXI-CON-900-01 Rev. A / January 2007
•
KPXI-SYS-6-250, 6-slot 3U PXI Instrument chassis
•
KPXI-SYS-8-400, 8-slot 3U PXI Instrument chassis
•
KPXI-SYS-14-500, 14-slot 3U PXI instrument chassis
•
KPXI-SYS-18-460X2, 18-slot 3U PXI Instrument chassis
•
Support Intel Architecture with Dynamic Execution
•
On-die, primary 32-KB instruction cache and 32-KB write-back data cache
•
On-die, 1-MB second level cache with Advanced Transfer Cache Architecture
•
Advanced Branch Prediction and Data Prefetch Logic
•
Streaming SIMD Extensions 2 (SSE2)
•
400-MHz, Source-Synchronous processor system bus
•
Advanced Power Management features including Enhanced Intel SpeedStep® technology
•
Single channel of x72, unbuffered, ECC DDR SDRAM (SO-DIMM)
•
200, 266MHz and 333MHz DDR device
•
64-bit data interface(72-bit with ECC)
•
Up to two double-sided SO-DIMMs (four rows populated) with unbuffered PC2100/PC2700
DDR-SDRAM (with or without ECC)
•
Up to 16 simultaneous open pages
•
64MB, 128MB, 256MB, and 512MB technologies for x8 and x16 width devices
•
System memory supports up to 2GB
•
SDRAM speed, type and size can be determined by the BIOS reading the SO-DIMM
presence detect bits on the System Management Bus (SMBus)
•
SDRAM timing register, which provides the DRAM speed control for the entire array, is
programmed to use the timings of the slowest DRAMs installed.
Return to
®
Pentium
Section Topics
Section 1: Introduction
®
M Processor with 1MB L2 cache in
1-5
Advertisement
Table of Contents
