Dram Data Integrity Mode - Keithley KPXI User Manual

Appendix B: Award BIOS Setup Utility
Figure B-5
Advanced chipset features
NOTE

DRAM Data Integrity Mode

This item will be show-only when user plugs non-ECC DRAM on memory slot. When user uses
DRAM with ECC, the data integrity mode can be selected as following description:
• ECC: DRAM with 72bit wide.
• Non-ECC: DRAM with 64bit wide.
MGM Core Frequency
This field is used to select the memory clock speed of the DIMM. The system board supports
DDR266, DDR333 or DDR400 when using 800MHz FSB CPU. DDR333 will run at 320MHz
memory frequency when used with 800MHz FSB CPU. Under such circumstance, make sure this
field is set to Auto or DDR320. Refer to chapter 1 (System Memory section) for detailed
specification of the memory supported by the system board.
System BIOS Cacheable
When this field is enabled, accesses to the system BIOS ROM addressed at F0000HFFFFFH are
cached, provided that the cache controller is enabled. The larger the range of the Cache RAM, the
higher the efficiency of the system.
Video BIOS Cacheable
As with caching the system BIOS, enabling the Video BIOS cache will allow access to video BIOS
address at C0000H to C7FFFH to be cached, if the cache controller is also enabled. The larger the
range of the Cache RAM, the faster the video performance.
B-10
The settings on the screen are for reference only. Your version may not be identical to
this one.
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KPXI System Controller User's Manual
KPXI-CON-900-01 Rev. A / January 2007