Xv-8100Cb And Ais328Dq - Furuno GV-86 User Manual

4.7 XV-8100CB and AIS328DQ

VCCI_3V0
VCCI_3V3
(*1)
RESET
(*1)
SCL
(*1)
SDA
I/O signal
RESET
SCL
SDA
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U2
VCC_3V0
1 4
VOUT VIN
(*4)
2 3
VSS CE
XC8101AA01-GR-G
U3
VCC_3V3
1 4
VOUT VIN
(*4)
2 3
VSS CE
XC8101AA01-GR-G
U5
1
ADDR
VCCI_3V3
2
GND
3
VDD
C6
LM73CIMKX-0
0.1uF
Description
External reset signal
I2C clock
I2C address/data bus
Figure 4.7 Reference Circuit of XV-8100CB and AIS328DQ
eRideOPUS 6/ eRideOPUS 7 GV-86/ GV-87
VCCI_3V3
(*3)
(*3)
R3 R4
10k 10k
6
SMBDAT
(*7)
5
ALERT_N
4
SMBCLK
Interface connection destination
eRideOPUS 6/7
NRST
TXD2_SCL
RXD2_SDA
10
Dead Reckoning User's Guide
SE16-900-002-00
VCCI_3V0
U1
1 8
NC VDD
C1
2 7
NC NC
0.1uF
(*7)
3 6
NC VREF
4 5
GND VOUT
XV-8100CB
3.3k R1 3.3k R2
C2
C3
2.2uF 2.2uF
U4
1 6
Vin+ Vin-
VCCI_3V0
2 5
(*7)
GND VDD
C5
3 4
SCL SDA
0.1uF
ADS1100A3IDBVT
GV-86/ 87
RST_N
TXD2_SCL
RXD2_SDA
C4
0.1uF