Itg-3500 And Ais328Dq - Furuno GV-86 User Manual

4.4 ITG-3500 and AIS328DQ

(*1)
RESET
(*1)
SCL
(*1)
SDA
I/O signal
RESET
SCL
SDA
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U1
VCC
1 4
VOUT VIN
(*4)
2 3
VSS CE
XC8101AA01-GR-G
VCC
(*3) (*3)
R1 R2
10k 10k
Description
External reset signal
I2C clock
I2C address/data bus
Figure 4.4 Reference Circuit of ITG-3500 and AIS328DQ
eRideOPUS 6/ eRideOPUS 7 GV-86/ GV-87
(*2)
(*2)
VCC
C1
0.01uF
U7
1
NC
2
NC
3
INT_2
4
Reserv ed
5
VDD
C4 C5
6
GND
0.1uF 10uF
Interface connection destination
eRideOPUS 6/7
NRST
TXD2_SCL
RXD2_SDA
7
Dead Reckoning User's Guide
SE16-900-002-00
U2
1
SDA/SDI GND
2
NC NC
3
VDDIO INT
4
/CS VDD
ITG-3500
C3
0.1uF
18
NC
17
NC
16
SDI/SDO/SDA
15
SDO/SA0
14
VDD_IO
13
Reserv ed
AIS328DQ
GV-86/ 87
RST_N
TXD2_SCL
RXD2_SDA
12
11
10
9
C2
0.1uF
(*2)
VCC