Xv-4001Bc And Ais328Dq - Furuno GV-86 User Manual

4.3 XV-4001BC and AIS328DQ

(*1)
SDA
(*1)
SCL
(*1)
RESET
I/O signal
RESET
SCL
SDA
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VCC
(*3) (*3)
R2 R1
10k 10k
U2
(*2)
VCC
1 4
VOUT VIN
(*4)
2 3
VSS CE
XC8101AA01-GR-G
Description
External reset signal
I2C clock
I2C address/data bus
Figure 4.3 Reference Circuit of XV-4001BC and AIS328DQ
eRideOPUS 6/ eRideOPUS 7 GV-86/ GV-87
(*2)
VCC
C2 C1
10uF 0.1uF
U3
1
NC
2
NC
3
INT_2
4
Reserv ed
5
VDD
6
C4 C3
GND
0.1uF 10uF
Interface connection destination
eRideOPUS 6/7
NRST
TXD2_SCL
RXD2_SDA
6
Dead Reckoning User's Guide
SE16-900-002-00
U1
1 10
Reserv ed Reserv ed
2 9
SCL SDA
3 8
SS MOSI
4 7
VDD GND
5 6
Reserv ed Reserv ed
XV-4001BC
NC
NC
SDI/SDO/SDA
SDO/SA0
VDD_IO
Reserv ed
AIS328DQ
GV-86/ 87
RST_N
TXD2_SCL
RXD2_SDA
18
17
16
(*2)
15
VCC
14
13