Major Components; Cpu Chip; I/O Combination; Port Addressing - David Griffith P112 Assembly And Operation Manual

Revision 1.1
Table of Contents

Advertisement

8

Major Components

The principal components are briefly introduced below, with particular reference
to their use in the present application.
8.1

CPU Chip

The Z80182 provides a Z180 CPU core, multi-function serial IO port, and two
DMA channels. Extensive use is made of the Z180's memory mapping ability,
to fill in "holes" in the physical address space, and to switch the ROM in and
out of circuit. This part is available in several speed grades: the initial build
will be fitted for 16MHz clocking.
8.2

I/O Combination

Most of the IO functions are implemented in a SMC multi-IO part, designed for
use in PC's. The board is multi-capable, and can accept any of the following
parts:
• FDC37C651
• FDC37C652
• FDC37C665
• FDC37C666
The '651 and '665 are fully software configurable. However the '652 and '666
have some functions configured by external resistors. These are not otherwise
fitted, and are the only surface-mount resistors on the board. Space limitations
preclude putting reference designators on the board, however they are all 1206
size, 27k parts. Their reference designators are R101..R111. No harm will occur
if they are fitted with a software-configurable IO chip.
These parts can be programmed to generate active-high or active-low interrupt
signals. In this application, active-low is required, and is selected by the start-up
code.
8.2.1

Port Addressing

The IO chip may be configured for several different internal address decoding
schemes, correponding to different IO assignments in a PC environment. In the
present application, the following addresses are used:
36

Advertisement

Table of Contents
loading

Table of Contents