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7.5
Expansion Socket
The CPU bus is brought out to the expansion socket J1. Access to expansion
memory has been described above. For external IO devices, /IORQ low and /M1
high should be decoded to validate an IO access. Valid addresses for expansion
boards are in the ranges 40. . .7F and C0. . .D7. The IO data strobes are /RD
and /WR.
Support is provided for expansion boards using the Z80182 internal DMA. The
/EXTRQ request line may be jumpered (at P2) to one of the internal DMA
channels.
7.6
Multi-I/O Chip
The non-CPU IO functions are implemented in an SMC multi-function IO chip.
These parts are available in several variants, and the board is designed to accept
4 different types: FD37C651, '652, '665 and '666. Further details on configura-
tion options are given below.
7.6.1
Address Decoding
The multi-IO chip occupies the IO address space 80. . .BF. These addresses are
mapped to appear to the IO chip as standard PC addresses. Programming of
the multi-IO features follows standard PC practice. The address mapping is
described below.
7.6.2
Cycle Timing
The IO chip latches address data at the beginning of /IOR or /IOW. This can
cause problems with the Zilog timing, which regards the /RD and /WR signals
as basically clock-enables. This is overcome by use of the CPU's "E" clock
output, which goes high during the valid part of a bus cycle. This is used as
a local enable to /IOR and /IOW, via the decoder U11A. This decoder also
provides the interlock from the safety-latch described below.
7.6.3
Safety Latch
As pointed out by Claude Palm (The Computer Journal, No. 76) the Z180-series
devices can generate spurious IO selections during interrupt-acknowledge cycles.
These are normally suppressed, since neither of the /RD or /WR data strobes
appear. However systems which decode the /DACK (DMA acknowledge) from
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