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7.1.2
Parallel Port
The Z80182 has one 8-bit parallel port available (the others have been overrid-
den for other functions). This is used to support on-board facilities. The pin
assignments are:
A0 RTC data I/O line (bidirectional)
A1 RTC Clock line
A2 RTC Reset line
A3..A4 Not used
A5 Set low to enable the 12V Vpp generator for flash ROMs
A6 DSR input from Serial Port 1
A7 RTS output to Serial Port
7.1.3
DMA
By default, DMA Channel 0 is used for the diskette controller, and Channel 1 is
available to an expansion card (if fitted). Jumper P2 may be altered if required,
to provide DMA support for Serial Port 1.
The Z180 DMA only provides the TENDx (end-of-block) signal during its write
cycle. This makes it unusable with the floppy disk controller, when reading from
the disk (the FDC requires TEND asserted during the DMA cycle addressed
to it, not to the memory). Consequently, the FDC is programmed not to use
TENDx, which implies that all transfers will post a "end of cylinder" error.
This is allowed for by the software.
7.1.4
Memory Mapping
The Z80182 includes two levels of memory mapping logic. The first maps the
64kB logical address space into a maximum of 3 "zones" in the 1MB physical
address space. The second decodes the /RAMCS and /ROMCS outputs from
the translated physical address.
In normal use, the first map may be changed frequently, as the operating system
switches tasks. The second will normally be initialised at reset, in terms of the
amount of memory actually fitted, and not changed thereafter. The boot-code
includes a "smart" memory initialisation routine, which examines the chips
actually fitted, and locates them in the physical space in an optimal manner.
The sign-on message includes a report of the amount of RAM available, and its
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