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7.2.2
On-Board RAM
Each RAM socket may accept a 32kB, 128kB or 512kB SRAM part. The address
decoding must be set for the parts in use, as follows:
RAM size
RAM part (typical)
32kB/64kB
HM62256
128kB/256kB
HM628128
512kB/1MB
HM628512
It is not pussible to mix RAM chips of different sizes.
For zero wait-state operation, 70-nanosecond parts are required.
7.2.3
Expansion RAM
Provision is made for an expansion board to carry up to 32kB of RAM, which
may be mapped into the main memory space. By convention, such memory will
be at the top of the 1MB physical space. The purpose of this is to provide for
dual-port memory for video drivers and similar devices. Of course, the 32kB
may be extended by a bank-switching arrangement on the expansion board.
Expansion board memory should be selected when the signals /ROMCS and
/RAMCS are both high (ie no on-board memory is selected). The read and
write enables are /MRD and /MWR, which enable bus transactions.
If necessary, the /WAIT line may be driven low to delay the CPU.
7.3
IO Cycle Control
The multi-function IO chip requires two additional wait-states in every IO cycle,
to satisfy its timing. This is provided by setting the IWI bits in the DCNTL
register of the Z801821 CPU (IO address 32H).
7.4
Real-Time Clock
The Dallas DS1302 has a simple bit-serial interface. This is supported by 3 bits
from the CPU's internal PIO device (see above). The DS1302 also provides
a block of battery-backed RAM, which may be useful for storing BIOS setup
parameters (memory size, serial communications setups, etc.).
P1 setting
P13 setting
1-4(A15)
1-2(Vcc)
1-2(A17)
1-2(Vcc)
1-3(A19)
2-3(A17)
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