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7
Logic Description
The following descriptions should be read in conjunction with the accompa-
nying schematics. Data sheets on the various chips are obtainable from the
manufacturers' web sites.
7.1
CPU
Zilog recommend two parts for new designs: the Z84C15 and Z80182. For the
present project, the Z80182 is appropriate, providing a Z180 core, with enhanced
memory mapping features. This part is available in a range of clock speeds: the
initial boards are clocked at 16MHz. This speed, while the highest the CPU
chip can support, does limit the choice of serial-port speeds, as it does not
factor well. This has minimal impact on the standard serial port, which uses
the in-built baud-rate generator. This generator is very flexible in its range of
possible divisors. If however, the expansion ports (see P16 below) are used,
they have a much reduced set of divisors available, and will normally require a
carefully-chosen clock frequency. The boot software can recognise and adjust to
the following clocks:
• 12.288MHz
• 16.0MHz
• 18.432MHz
• 24.576MHz
The last two will require a faster CPU chip to be fitted.
The Z80182 includes several in-built peripheral functions. All these are fully
supported by the Z80 vectored interrupt system. The following internal periph-
erals are used:
7.1.1
Serial Port
The Z80182 has a total of 4 serial ports. Of these, one is brought out as the
default terminal port, at normal RS232 levels. The remaining 3 ports are avail-
able as un-buffered TTL signals, for use with off-board level converters. One of
these additional ports features full SDLC functionality, and can be configured
for DMA control.
The Z80182 serial ports do not support the DSR and RTS modem-control sig-
nals, so these are provided (in the main-terminal port) by two lines from the
on-chip parallel port (see below). These lines are not used by the standard
software.
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