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the address may malfunction, due to these spurious /IORQ signals. In the
present design, this is prevented by the latch U8.
This is set at the beginning of a interrupt acknowledge cycle (/M1 and /IORQ
both low), and blocks any address decodes. The latch is only cleared when
/IORQ again goes high, at the end of the acknowledge cycle.
7.7
Serial Port 2
This is the "primary" serial port on the multi-IO device (the secondary port is
not used). It is strictly PC compatible.
7.8
Diskette Port
The diskette interface emulates a standard PC-type diskette controller. The IO
chip is configured to logically "swap" Drives 0 and 1. This assumes the drives
have the DS1 jumper set, as is normal for PC-AT usage. Given this, Drive-0
connects directly to the PCB, with no ribbon-cable cores swapped. This is to
enable the PCB to be mounted directly on the disk drive, with the PCB and
drive connectors adjacent. Drive-1 will be the further away, and will have cores
10-16 swapped in the cable.
It should be noted that there is no universal standard regarding the placement
of the data connector on diskette drives: it is not possible to have this card fit
directly to every drive available. The direct fitting has been tested with Teac
FD235 drives.
7.9
Printer Port
The printer port provides PC-like functions, in basic bidirectional mode. En-
hanced ECP and EPP modes are not supported.
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