Sdram Interface Signals - Daewoo DVDP485 Service Manual

PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE
SA[7:0]/GPA[15:
8]
SA[15:8]
INTS#
INTM#
WR#
RD#

4.3 SDRAM Interface Signals

Pin name Type
MA[11:0]
BS[1:0]
MD[15:0] I/O
SDCLKO
SDCLKI
SCS#
RAS#
CAS#
SWE#
DQM
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I/O When LATS=1, SA[7:0] input is specified, representing the low byte
address bus, input.
When LATS=0, two options: one is SA[7:0] output of the low byte
address latched from SAD[7:0] input by ALE; the other is GPA[15:8],
general purpose IO bus A bits[15:8], bi-directional; SA[7:0] output is
default.
I The high byte of the address bus.
O Interrupt request of servo, active low.
O Interrupt request of AV decoder, active low.
I Write enable, active low.
I Read enable, active low.
Description
O SDRAM Address bus output
O SDRAM Bank Select output
SDRAM Data bus keeps as input state except for WRITE operation
O SDRAM Clock Output
I SDRAM Clock Input
O SDRAM Chip Select output, active Low
O Row Address Strobe output, active Low
O Column Address Strobe output, active Low
O Write Enable output, active Low
O SDRAM data mask, active HIGH
CTK CONFIDENTIAL, NO DISCLOSURE
Copyright (C) 2003 Cheertek Inc. All Rights Reserved.
CT908