Daewoo DVDP485 Service Manual page 19

PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE
PORT0 I/O
[7:0]
SA[7:0]/GP I/O
A[15:8]
PORT2 I/O
[7:0]
PORT1 I/O
[7:0]
The above information is the exclusive intellectual property of Cheertek Inc. and shall not be disclosed, distributed or reproduced without permission from Cheertek Inc.
Port0 is an 8-bit bi-directional I/O port.
In accesses to external memory, port0 outputs the low
byte of the external memory address,
time-multiplexed with the data byte being written or
read.
SA[7:0]: lower address byte for external program and
data memories, latched by ALE from Port0 address
phase, output. This is the default. Optionally these
pins can be used as general purpose IO signals.
GPA[15:8]: general purpose IO bus A bits[15:8],
bi-directional.
Port2 is an 8-bit bi-directional I/O port with internal
pull-up. Port2 also serves as memory address bus.
In accesses to external memory, port2 outputs the
high byte of the external memory address.
Port1 is an 8-bit bi-directional I/O port with internal
pull-up.
P1.0 and p1.1 also serve the T2 and T2EX functions,
respectively.
P1.2 and P1.3 also serve the RXD2 and TXD2,
respectively.
P1.4: GPA7, general purpose IO bus A bit 7, initial in
input state
P1.5, P1.6 and P1.7 also serve external interrupt
inputs
CTK CONFIDENTIAL, NO DISCLOSURE
SAD[7:0]: low byte address
and data bus, bi-directional.
LATS=1, SA[7:0]: low byte
address bus, input.
LATS=0, SA[7:0] output or
GPA[15:8] selected by register
SA[15:8]: high byte address
bus, input.
P1.4: INTS#, output
Copyright (C) 2003 Cheertek Inc. All Rights Reserved.
CT908