Pin Description - Daewoo DVDP485 Service Manual

PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE

4. Pin Description

4.1 System Operation Signals and Power/Ground
Pin name
OSCI
OSCO
RESET#
EMU
GPA[3:0]/PD[7:4]
VLFM
VLFA
AVD18 (2)
AVSSP (2)
VDDP (9)
VSSP (9)
VDD (9)
VSS (9)
4.2 Micro-controller Interface Signals
Pin name Type
ALE I/O
PSEN# I/O
The above information is the exclusive intellectual property of Cheertek Inc. and shall not be disclosed, distributed or reproduced without permission from Cheertek Inc.
Type Description
I Clock input. It can be oscillator or crystal input. Frequency is 27MHz.
O Output terminal for crystal connection. This signal also emulates as VCLK for
digital video pixel clock output
I System reset, active LOW
I Emulation mode select
EMU =0, normal operation, enable internal
micro-controller,
=1, select emulation mode, disable internal
micro-controller.
I/O General purpose IO bus A bits[3:0], initial in input state/digital video pixel data
bits[7:4] output; GPA[3:0] by default
AI MPLL loop filter, connect to a capacitor
AI APLL loop filter, connect to a capacitor
AP 1.8V analog power supply for MPLL and APLL
AG Analog ground for MPLL and APLL
DP 3.3V digital power supply for IO driving buffer
DG Digital ground for IO driving buffer
DP 1.8V digital power supply for core and IO pre-buffer
DG Digital ground for core and IO pre-buffer
Internal uC mode (EMU=0)
Address latch enable output. It is used to latch the
address low byte expressed on port0.
Program strobe enable output. It is used to strobe code
of the external program memory.
CTK CONFIDENTIAL, NO DISCLOSURE
External uC mode (EMU=1)
ALE: Address latch enable
input.
LATS: Low byte address
conveying type select input.
LATS=0, mux with SAD[7:0];
LATS=1, conveyed on
SA[7:0]
Copyright (C) 2003 Cheertek Inc. All Rights Reserved.
CT908