Analog Devices EVAL-AD5761RSDZ User Manual page 13

EVAL-AD5761RSDZ
RESET
LDAC
LK2
R36
+5V
DNP
C35
0.1µF
R35
0Ω
User Guide
J1
60
RESET_IN
59
UART_RX
58
GND
57
RESET_OUT
56
SDP
TWI_A0
55
STANDARD
NC
54
CONNECTOR
NC
53
NC
52
GND
51
NC
50
NC
49
*
TMR_C
48
TIMERS
TMR_A
47
GPIO6
46
GND
45
GENERAL
GPIO4
44
INPUT/OUTPUT
GPIO2
43
GPIO0
42
SCL_1
41
I2C
SDA_1
40
GND
39
SPI_SEL1/SPI_SS
38
SPI_SEL_C
37
SPI
SPI_SEL_B
36
GND
35
SPORT_INT
34
*
SPI_D3 SPORT_TSCLK
33
SPI_D2 * SPORT_DT0
32
SPORT
SPORT_DT1 SPORT_TFS
31
SPORT_DR1 SPORT_RFS
30
*
SPORT_TDV1 SPORT_DR0
29
*
SPORT_TDV0 SPORT_RSCLK
28
GND
27
PAR_FS1
26
PAR_FS3
25
PAR_A1
24
PAR_A3
23
GND
22
PAR_CS
21
PAR_RD
20
PAR_D1
19
PARALLEL
PAR_D3
18
PORT
PAR_D5
17
GND
16
PAR_D7
15
PAR_D9
14
PAR_D11
13
PAR_D13
12
PAR_D14
11
GND
10
*
PAR_D17
9
*
PAR_D19
8
*
PAR_D21
7
*
PAR_D23
6
GND
5
USB_VBUS
4
GND
3
GND
2
NC
1
VIN *NC on BLACKFIN SDP
DGND
Figure 12. Schematic of the
61
BMODE1
62
UART_TX
63
GND
64
R24
SLEEP
65
100kΩ
WAKE
66
NC
67
NC
68
NC
69
GND
70
NC
71
CLK_OUT
72
TMR_D
73
TMR_B
74
GPIO7
75
GND
76
GPIO5
77
GPIO3
78
GPIO1 CLR
79
SCL_0
80
SDA_0
81
GND
82
SPI_CLK
83
SPI_MISO
84
SPI_MOSI
85
SPI_SEL_A
86
GND
87
SCLK
88
SDIN
89
90
SYNC
91
SDO
92
93
GND
94
PAR_CLK
95
PAR_FS2
96
PAR_A0
97
PAR_A2
98
GND
99
PAR_INT
100
PAR_WR
101
PAR_D0
102
PAR_D2
103
PAR_D4
104
GND
105
PAR_D6
106
PAR_D8
107
PAR_D10
108
PAR_D12
109
GND
110
PAR_D15
111
*
PAR_D16
112
*
PAR_D18
113
*
PAR_D20
+3.3V
114
*
PAR_D22
115
GND
116
VIO(+3.3V)
117
GND
118
GND
119
NC
120
NC
DGND
EVAL-SDP-CB1Z SDP-B Board Connector
Rev. 0 | Page 13 of 17
+3.3V
R18
+3.3V
DNP
U4
1 8
A0 VCC
2 7
A1 WP
3 6
A2 SCL
4 5
VSS SDA
R25
24LC64-I/SN
100kΩ
J5
PMOD12
1
SYNC 12
2 11
SDIN
3 10
SDO
4 9
SCLK
5 8
DGND
6 7
+3.3V
UG-1151
+3.3V
DGND
CLR
LDAC
RESET