Integra DTR-5.9 Service Manual page 66

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-29
Q8001 : FLI30502 (LCD TV Controller with Worldwide Standard Sound Processor
and HDMI Receiver)-11/12
TERMINAL DESCRIPTION
Digital Power and Ground
Pin Name
RVDD_3.3
CVDD_1.8
CRVSS
OCM JTAG
Pin Name
JTAG_CLK
JTAG_MODE
JTAG_RESET
JTAG_TDO
JTAG_TDI
Pin # I/O Description
30
47
P
110 Ring VDD. Connect to digital 3.3 V.
128
152
172
20
26
37
P
43 Core VDD. Connect to digital 3.3V.
51
65
103
131
134
143
158
21
27
31
38 G Chip ground for core and ring.
44
48
52
66
104
111
129
132
135
144
153
159
Pin # I/O Description
22 I JTAG CLOCK signal
O
23 JTAG Mode signal
I
49 JTAG RESET aignal
I
154 JTAG DATA OUT signal
155 I JTAG DATA IN signal
DTR-5.9