Pll Controller Divider 2 Register (Plldiv2); Pll Controller Divider 2 Register (Plldiv2) Field Descriptions - Texas Instruments TMS320DM355 User Manual

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6.6.7 PLL Controller Divider 2 Register (PLLDIV2)

The PLL controller divider 2 register (PLLDIV2) is shown in
PLLC1 and PLLC2. PLLDIV2 controls the divider for SYSCLK2. The divider for PLLC1 SYSCLK2 is fixed
(cannot be changed) to (/4). The divider for PLLC2 SYSCLK2 is fixed (cannot be changed) to (/2). For
PLLC1 and PLLC2, the divider must always be enabled (bit D2EN=1).
31
15 14
D2EN
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-10. PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions
Bit Field
31-16 Reserved
15 D2EN
14-5 Reserved
4-0 RATIO
SPRUFB3 – September 2007
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Figure 6-9. PLL Controller Divider 2 Register (PLLDIV2)
Reserved
R-0
R-0
Value Description
Reserved
Divider enable for SYSCLK2. For PLLC1 and PLLC2, this bit must always be set to 1.
0 Disable
1 Enable
Reserved
Divider ratio for SYSCLK2. Ratio value = RATIO + 1
Figure 6-9 and described in
Reserved
R-0
R-0
5
PLL Controller Register Map
Table 6-10
4
RATIO
R-3
R-1
PLL Controllers (PLLCs)
for
16
0
51