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6.6.5 PLL Pre-Divider Control Register (PREDIV)
The PLL pre-divider control register (PREDIV) is shown in
PLLC1 and PLLC2. For PLLC1, the pre-divider ratio is fixed (cannot be changed) to 8. For PLLC2, the
pre-divider ratio defaults to 8, however, it may be changed to allow for lower frequencies.
31
15
14
PREDEN
R-1
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-16
Reserved
15
PREDEN
14-5
Reserved
4-0
RATIO
SPRUFB3 – September 2007
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Figure 6-7. PLL Pre-Divider Control Register (PREDIV)
Reserved
R-0
R-0
Table 6-8. PLL Pre-Divider Control (PREDIV) Field Descriptions
Value
Description
Reserved
Pre-divider enable. For PLLC1 and PLLC2, this bit must always be set to 1.
0
Disable
1
Enable
0
Reserved
Divider ratio for post divider. Ratio value = RATIO + 1
Figure 6-7
and described in
Reserved
R-0
R-0
5
PLL Controller Register Map
Table 6-8
for
4
RATIO
R-7
R/W-7
PLL Controllers (PLLCs)
16
0
49
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