Register Definitions - Dynamic Engineering PMC-PARALLEL-TTL User Manual

Register Definitions

pmcparttl_BASE
[$00 parallel-io Control Register Port read/write]
DATA BIT
31-20
19
18
17
16
15-5
4
3
2
1
0
Figure 4 PMC-PARALLEL-TTL Control port 0 Bit Map
This is the base control register for the PMC Parallel TTL. The features common to all
channels are controlled from this port. Unused bits are reserved for additional new
features. Unused bits should be programmed '0' to allow for future commonality.
Master Interrupt Enable when '1' gates active interrupt requesting conditions onto
Interrupt Request A. When set to '0' the interrupting functions are available as status
but no interrupt request is generated by the card to allow for polled operation.
Force Interrupt when '1' and the master is enabled will cause an interrupt request. The
interrupt can be cleared by clearing this bit or disabling the master interrupt enable or
both. Force Interrupt is used for test and software development purposes.
Master Parallel Data Enable is used to allow the upper and lower data to be
synchronized. The upper 32 bits and the lower 32 bits are not accessed at the same
time. If the user wants to have the upper and lower data change at the same time the
Master enable can be cleared to '0', both halves of the data written and then the enable
set '1'. If synchronization is not an issue program to '1' as part of initialization.
The PLL functions are not currently installed on the base model. The bits are reserved
for future applications that may require the PLL.
DESCRIPTION
spare
pll_dat
pll_s2
pll_sclk
pll_en
spare
Master Parallel Data Enable
spare
spare
Force Interrupt
Master Interrupt Enable
Embedded Solutions Page 13