Address Map - Dynamic Engineering PMC-PARALLEL-TTL User Manual

Address Map

Function
// PMC Parallel TTL definitions
#define pmcparttl_BASE
#define pmcparttl_ID
#define pmcparttl_STATUS
#define pmcparttl_DirL
#define pmcparttl_DirU
#define pmcparttl_DatL
#define pmcparttl_DatU
#define pmcparttl_DatLreg
#define pmcparttl_DatUreg
#define pmcparttl_COSclk
//#define spare
#define pmcparttl_RisLreg
#define pmcparttl_RisUreg
#define pmcparttl_FallLreg
#define pmcparttl_FallUreg
#define pmcparttl_IntRisLreg
#define pmcparttl_IntRisUreg
#define pmcparttl_IntFallLreg
#define pmcparttl_IntFallUreg
#define pmcparttl_IntRisLstat
#define pmcparttl_IntRisUstat
#define pmcparttl_IntFallLstat
#define pmcparttl_IntFallUstat
Figure 3 PMC-PARALLEL-TTL Internal Address Map
The address map provided is for the local decoding performed within PMC-Parallel-TTL.
The addresses are all offsets from a base address. The carrier board that the PMC is
installed into provides the base address. Dynamic Engineering prefers a long-word
oriented approach because it is more consistent across platforms.
The map is presented with the #define style to allow cutting and pasting into many
compilers "include" files.
The host system will search the PCI bus to find the assets installed during power-on
initialization. The VendorId = 0x10EE and the CardId = 0x2C for the PMC-Parallel-TTL.
Offset
0x0000 // 0 PMC Parallel TTL base control register offset
0x0004 // 1 PMC Parallel TTL ID Register offset
0x0008 // 2 PMC Parallel TTL status Register offset
0x000c // 3 PMC Parallel TTL Direction lower Register offset
0x0010 // 4 PMC Parallel TTL Direction upper Register offset
0x0014 // 5 PMC Parallel TTL Data lower Register, line data read
0x0018 // 6 PMC Parallel TTL Data upper Register, line data read
0x001c // 7 PMC Parallel TTL Data lower Register read-back
0x0020 // 8 PMC Parallel TTL Data upper Register read-back
0x0024 // 9 PMC Parallel TTL COS Clock definition Register
0x0028 // 10 PMC Parallel TTL
0x002c // 11 PMC Parallel TTL Rising lower Register
0x0030 // 12 PMC Parallel TTL Rising upper Register
0x0034 // 13 PMC Parallel TTL Falling lower Register
0x0038 // 14 PMC Parallel TTL Falling upper Register
0x003c // 15 PMC Parallel TTL Interrupt Enable Rising lower Register
0x0040 // 16 PMC Parallel TTL Interrupt Enable Rising upper Register
0x0044 // 17 PMC Parallel TTL Interrupt Enable Falling lower Register
0x0048 // 18 PMC Parallel TTL Interrupt Enable Falling upper Register
0x004c // 19 PMC Par TTL Interrupt Rising LWR Stat Rd, write = clear
0x0050 // 20 PMC Par TTL Interrupt Rising UPR Stat Rd, write = clear
0x0054 // 21 PMC Par TTL Interrupt Falling LWR Stat Rd, write = clear
0x0058 // 22 PMC Par TTL Interrupt Falling UPR Stat Rd, write = clear
Embedded Solutions Page 11