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Renesas R8C/20 Hardware Manual

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REJ09B0250-0200

16

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Technology Corp. without notice. Please review the latest information published

by Renesas Technology Corp. through various means, including the Renesas Technology

Corp. website (http://www.renesas.com).

Rev.2.00

Revision Date: Aug 27, 2008

R8C/20

, R8C/21

Group

R8C FAMILY / R8C/2x SERIES

Group

Hardware Manual

RENESAS MCU

www.renesas.com

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Summary of Contents for Renesas R8C/20

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp.
Page 2 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 3 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 4 The following documents apply to the R8C/20 Group and R8C/21 Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site.
Page 5 Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,”...
Page 6 Register Notation The symbols and terms used in register diagrams are described below. XXX Register Symbol Address After Reset Bit Symbol Bit Name Function b1 b0 XXX bits XXX0 1 0: XXX 0 1: XXX 1 0: Do not set. XXX1 1 1: XXX Nothing is assigned.
Page 7 List of Abbreviations and Acronyms Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment Bus Input / Output IrDA Infrared Data Association Least Significant Bit...
Page 8: Table Of Contents
Stack Pointer Select Flag (U) ......................12 2.8.9 Processor Interrupt Priority Level (IPL) ..................... 12 2.8.10 Reserved Bit ............................12 Memory ............................13 R8C/20 Group ............................13 R8C/21 Group ............................14 Special Function Registers (SFRs) ....................15 Resets ............................21 Hardware Reset ............................24 5.1.1 When Power Supply is Stable ......................
Page 9 6.1.2 Monitoring Vdet2 ..........................34 Voltage Monitor 1 Reset ......................... 35 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset ..............36 Programmable I/O Ports ....................... 38 Functions of Programmable I/O Ports ..................... 38 Effect on Peripheral Functions ........................ 39 Pins Other than Programmable I/O Ports ....................
Page 10 12.1.4 Peripheral Function Interrupt ......................89 12.1.5 Interrupts and Interrupt Vector ......................90 12.1.6 Interrupt Control ..........................92 12.2 INT Interrupt ............................101 12.2.1 INTi Interrupt (i = 0 to 3) ........................101 12.2.2 INTi Input Filter (i = 0 to 3) ......................103 12.3 Key Input Interrupt ..........................
Page 11 14.4.1 Output Compare Mode ........................258 14.4.2 Notes on Timer RE ........................... 264 Serial Interface ..........................265 15.1 Clock Synchronous Serial I/O Mode ..................... 271 15.1.1 Polarity Select Function ........................274 15.1.2 LSB First/MSB First Select Function ....................274 15.1.3 Continuous Receive Mode ........................
Page 12 18.4 A/D Conversion Cycles ......................... 371 18.5 Internal Equivalent Circuit of Analog Input ..................372 18.6 Output Impedance of Sensor Under A/D Conversion ................373 18.7 Notes on A/D Converter ........................374 Flash Memory ..........................375 19.1 Overview ............................... 375 19.2 Memory Map ............................
Page 13 21.8 Notes on Flash Memory ........................448 21.8.1 CPU Rewrite Mode ........................... 448 21.9 Notes on Noise ............................451 21.9.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch-up ............................451 21.9.2 Countermeasures against Noise Error of Port Control Registers ............. 451 Notes on On-Chip Debugger ......................
Page 14 SFR Page Reference Address Address Register Symbol Page Register Symbol Page 0000h 0040h 0001h 0041h 0002h 0042h 0003h 0043h 0004h 0044h Processor Mode Register 0 0005h 0045h Processor Mode Register 1 0006h 0046h System Clock Control Register 0 0007h 0047h System Clock Control Register 1 0008h 0048h...
Page 15 Address Address Register Symbol Page Register Symbol Page 0080h 00C0h A/D Register 0081h 00C1h 0082h 00C2h 0083h 00C3h 0084h 00C4h 0085h 00C5h 0086h 00C6h 0087h 00C7h 0088h 00C8h 0089h 00C9h 008Ah 00CAh 008Bh 00CBh 008Ch 00CCh 008Dh 00CDh 008Eh 00CEh 008Fh 00CFh 0090h...
Page 16 Address Address Register Symbol Page Register Symbol Page 0100h Timer RA Control Register TRACR 0140h Timer RD Control Register 0 TRDCR0 176, 191, 206, 218, 229, 243 0101h Timer RA I/O Control Register TRAIOC 121, 124, 127, 0141h Timer RD I/O Control Register A0 TRDIORA0 129, 131, 134 177, 192...
Page 17: Overview
With 1 Mbyte of address space, it is capable of executing instructions at high speed. This Furthermore, the data flash (1 KB x 2 blocks) is embedded in the R8C/21 Group. The difference between R8C/20 and R8C/21 Groups is only the existence of the data flash. Their peripheral functions are the same.
Page 18: Performance Overview
R8C/20 Group, R8C/21 Group 1. Overview Performance Overview Table 1.1 outlines the Functions and Specifications for R8C/20 Group and Table 1.2 outlines the Functions and Specifications for R8C/21 Group. Table 1.1 Functions and Specifications for R8C/20 Group Item Specification Number of fundamental instructions 89 instructions Minimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
Page 19 R8C/20 Group, R8C/21 Group 1. Overview Table 1.2 Functions and Specifications for R8C/21 Group Item Specification Number of fundamental instructions 89 instructions Minimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Page 20: Block Diagram
R8C/20 Group, R8C/21 Group 1. Overview Block Diagram Figure 1.1 shows a Block Diagram. I/O port Port P0 Port P1 Port P2 Port P3 Port P4 Port P6 System clock A/D converter Timer × generation circuit (10 bits 12 channels)
Page 21: Product Information
R8C/20 Group, R8C/21 Group 1. Overview Product Information Table 1.3 lists Product Information for R8C/20 Group and Table 1.4 lists Product Information for R8C/21 Group. Table 1.3 Product Information for R8C/20 Group Current of Aug. 2008 Type No. ROM Capacity...
Page 22 R8C/20 Group, R8C/21 Group 1. Overview Table 1.4 Product Information for R8C/21 Group Current of Aug. 2008 ROM Capacity Type No. RAM Capacity Package Type Remarks Program ROM Data Flash R5F21216JFP 32 Kbytes 1 Kbyte X 2 2 Kbytes PLQP0048KB-A...
Page 23: Pin Assignments
R8C/20 Group, R8C/21 Group 1. Overview Pin Assignments Figure 1.4 shows Pin Assignments (Top View). Pin assignments (top view) P0_6/AN1 P1_3/KI3/AN11 P0_5/AN2 P1_4/TXD0 P0_4/AN3 P1_5/RXD0/(TRAIO)/(INT1) P4_2/VREF P1_6/CLK0 P6_0/TREO P1_7/TRAIO/INT1 R8C/20 Group, P6_2 P2_0/TRDIOA0/TRDCLK R8C/21 Group P6_1 P2_1/TRDIOB0 P0_3/AN4 P2_2/TRDIOC0 P0_2/AN5...
Page 24: Pin Functions
R8C/20 Group, R8C/21 Group 1. Overview Pin Functions Table 1.5 lists the Pin Functions and Table 1.6 lists the Pin Name Information by Pin Number. Table 1.5 Pin Functions Type Symbol I/O Type Description Power Supply Input Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Page 25 R8C/20 Group, R8C/21 Group 1. Overview Table 1.6 Pin Name Information by Pin Number I/O Pin Functions for of Peripheral Modules Clock Synchronous Control Pin Port Serial C Bus Number Interrupt Timer Serial I/O Interface Converter Interface with Chip Select...
Page 26: Central Processing Unit (Cpu)
R8C/20 Group, R8C/21 Group 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB comprise a register bank. Two sets of register banks are provided.
Page 27: Data Registers (R0, R1, R2 And R3)
R8C/20 Group, R8C/21 Group 2. Central Processing Unit (CPU) Data Registers (R0, R1, R2 and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The same applies to R1H and R1L as R0H and R0L.
Page 28: Interrupt Enable Flag (I)
R8C/20 Group, R8C/21 Group 2. Central Processing Unit (CPU) 2.8.7 Interrupt Enable Flag (I) The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.
Page 29: Memory
Memory R8C/20 Group Figure 3.1 shows a Memory Map of R8C/20 Group. The R8C/20 Group has 1 Mbyte of address space from address 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM is allocated addresses 04000h to 0FFFFh.
Page 30: R8C/21 Group
R8C/20 Group, R8C/21 Group 3. Memory R8C/21 Group Figure 3.2 shows a Memory Map of R8C/21 Group. The R8C/21 Group has 1 Mbyte of address space from address 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM is allocated addresses 04000h to 0FFFFh.
Page 31: Special Function Registers (Sfrs)
R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs) Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Table 4.1 to Table 4.6 list the SFR Information. Table 4.1 SFR Information (1)
Page 32 R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs) Table 4.2 SFR Information (2) Address Register Symbol After reset 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h Timer RD0 Interrupt Control Register TRD0IC XXXXX000b 0049h Timer RD1 Interrupt Control Register...
Page 33 R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs) Table 4.3 SFR Information (3) Address Register Symbol After reset 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h...
Page 34 R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs) Table 4.4 SFR Information (4) Address Register Symbol After reset 00C0h A/D Register 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h...
Page 35 R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs) Table 4.5 SFR Information (5) Address Register Symbol After reset 0100h Timer RA Control Register TRACR 0101h Timer RA I/O Control Register TRAIOC 0102h Timer RA Mode Register TRAMR 0103h Timer RA Prescaler Register...
Page 36 R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs) Table 4.6 SFR Information (6) Address Register Symbol After reset 0140h Timer RD Control Register 0 TRDCR0 0141h Timer RD I/O Control Register A0 TRDIORA0 10001000b 0142h Timer RD I/O Control Register C0...
Page 37: Resets
R8C/20 Group, R8C/21 Group 5. Resets Resets There are resets: hardware reset, power-on reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and Sources. Table 5.1 Reset Names and Sources...
Page 38 R8C/20 Group, R8C/21 Group 5. Resets Table 5.2 lists the Pin Functions after Reset, Figure 5.2 shows CPU Register Status after Reset, Figure 5.3 shows Reset Sequence, and Figure 5.4 shows the OFS Register. Table 5.2 Pin Functions after Reset...
Page 39 R8C/20 Group, R8C/21 Group 5. Resets fOCO-S RESET pin 10 cycles or more are needed fOCO-S clock × 32 cycles Internal reset signal Start time of flash memory CPU clock × 28 cycles (CPU clock × 14 cycles) CPU clock...
Page 40: Hardware Reset
R8C/20 Group, R8C/21 Group 5. Resets Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the power supply voltage meets the recommended performance condition, the pins, CPU, and SFR are reset (refer to Table 5.2 Pin Functions after Reset).
Page 41 R8C/20 Group, R8C/21 Group 5. Resets 2.7 V RESET RESET 0.2 VCC or below td(P-R) + 10 µs or more NOTE: 1. Refer to 20. Electrical Characteristics. Figure 5.5 Example of Hardware Reset Circuit and Operation Power supply voltage detection circuit 2.7 V...
Page 42: Power-On Reset Function
R8C/20 Group, R8C/21 Group 5. Resets Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR. When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more.
Page 43: Voltage Monitor 1 Reset
R8C/20 Group, R8C/21 Group 5. Resets Voltage Monitor 1 Reset A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet1.
Page 44: Voltage Detection Circuit
R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Voltage Detection Circuit The voltage detection circuit is a circuit to monitor the input voltage to the VCC pin. This circuit monitors the VCC input voltage by the program. And the voltage monitor 1 reset, voltage monitor 2 interrupt and voltage monitor 2 reset can be used.
Page 45 R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit VCA27 Voltage detection 2 Noise filter signal Internal reference ≥ Vdet2 voltage VCA1 register VCA26 VCA13 bit Voltage detection 1 signal ≥ Vdet1 Figure 6.1 Block Diagram of Voltage Detection Circuit Voltage monitor 1 reset generation circuit...
Page 46 R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Voltage monitor 2 interrupt/reset generation circuit VW2F1 to VW2F0 = 00b = 01b Voltage detection 2 circuit = 10b VW2C2 bit is set to 0 (not detected) by writing 0 by program.
Page 47 R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Voltage Detection Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 Symbol Address After Reset 0031h 00001000b VCA1 Bit Symbol Bit Name Function — Reserved bits Set to 0...
Page 48 R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Voltage Monitor 1 Circuit Control Register b7 b6 b5 b4 b3 b2 b1 b0 After Reset Symbol Address VW1C 0036h The LVD1ON bit in the OFS register is set to 1: 0000X000b...
Page 49 R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Voltage Monitor 2 Circuit Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset VW2C 0037h Bit Symbol Bit Name Function Voltage monitor 2 interrupt/reset 0 : Disable...
Page 50: Vcc Input Voltage
R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit VCC Input Voltage 6.1.1 Monitoring Vdet1 Vdet1 cannot be monitored. 6.1.2 Monitoring Vdet2 Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has elapsed (refer to 20.
Page 51: Voltage Monitor 1 Reset
R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Voltage Monitor 1 Reset Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Reset and Figure 6.7 shows an Example of Voltage Monitor 1 Reset Operation. To use the voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter disabled).
Page 52: Voltage Monitor 2 Interrupt And Voltage Monitor 2 Reset
R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.8 shows an Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation. To use the voltage monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to 1 (digital filter disabled).
Page 53 R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Vdet2 2.7 V VCA13 bit Sampling clock of digital filter Sampling clock of digital filter x 4 cycles x 4 cycles VW2C2 bit Set to 0 by a program When the VW2C1 bit is set...
Page 54: Programmable I/O Ports
R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Programmable I/O Ports There are 41 programmable Input/Output ports (I/O ports) P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5, and P6. Also, P4_6 and P4_7 can be used as input-only ports if the XIN clock oscillation circuit is not used, and the P4_2 can be used as an input-only port if the A/D converter is not used.
Page 55: Effect On Peripheral Functions
R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Effect on Peripheral Functions Programmable I/O ports function as I/O of peripheral functions (refer to Table 1.6 Pin Name Information by Pin Number). Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 4, 6 j = 0 to 7).
Page 56 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Pull-up selection Direction register Data bus Port latch Analog input P1_0 to P1_3 Pull-up selection Direction register Output from each peripheral function Data bus Port latch Input to each peripheral function Analog input...
Page 57 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports P1_5 and P1_7 Pull-up selection Direction register Output from each peripheral function Data bus Port latch Digital INT1 input filter Input to each peripheral function P1_6 and P2 Pull-up selection Direction register...
Page 58 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports P3_0 and P3_1 Pull-up selection Direction register Output from each peripheral function Data bus Port latch P3_3 to P3_5 and P3_7 Pull-up selection Direction register Output from each peripheral function Data bus...
Page 59 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports P4_2/VREF Data bus P4_3 and P4_4 Pull-up selection Direction register Data bus Port latch NOTE: symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC. Figure 7.4 Configuration of Programmable I/O Ports (4) Rev.2.00 Aug 27, 2008...
Page 60 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports P4_5 Pull-up selection Direction register Data bus Port latch Digital INT0 and input to each peripheral function filter P4_6/XIN Data bus Clocked inverter P4_7/XOUT Data bus NOTES: symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC.
Page 61 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports P6_0 Pull-up selection Direction register Output from each peripheral function Data bus Port latch P6_1 to P6_5 Pull-up selection Direction register Data bus Port latch NOTE: symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC.
Page 62 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports P6_6 Pull-up selection Direction register Output from each peripheral function Data bus Port latch Digital INT2 input filter P6_7 Pull-up selection Direction register Data bus Port latch Digital INT3 input filter Input to each peripheral function NOTE: symbolizes a parasitic diode.
Page 63 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports MODE MODE signal input RESET RESET signal input NOTE: symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC. Figure 7.8 Configuration of I/O Pins Rev.2.00 Aug 27, 2008...
Page 64 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports (1,2) Port Pi Direction Register (i = 0 to 4, 6) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00E2h 00E3h 00E6h 00E7h 00EAh 00EEh Bit Symbol Bit Name...
Page 65 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Pull-Up Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00FCh PUR0 Bit Symbol Bit Name Function PU00 P0_0 to P0_3 pull-up 0 : Not pulled up...
Page 66: Port Settings
R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Port Settings Table 7.4 to Table 7.47 list the port settings. Table 7.4 Port P0_0/AN7 Register ADCON0 Function PD0_0 ADGSEL0 Input port Setting Output port value A/D converter input (AN7) X: 0 or 1 NOTE: 1.
Page 67 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Table 7.9 Port P0_5/AN2 Register ADCON0 Function PD0_5 ADGSEL0 Input port Setting Output port value A/D converter input (AN2) X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
Page 68 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Table 7.14 Port P1_2/KI2/AN10 Register KIEN ADCON0 Function PD1_2 KI2EN ADGSEL0 Input port Output port Setting value KI2 input A/D converter input (AN10) X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Page 69 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Table 7.18 Port P1_6/CLK0 Register U0MR Function PD1_6 SMD2 SMD1 SMD0 CKDIR Other than 001b Input port Setting value Other than 001b Output port CLK0 (external clock) input CLK0 (internal clock) output...
Page 70 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Table 7.21 Port P2_1/TRDIOB0 Register TRDOER1 TRDFCR TRDPMR TRDIORA0 Function PD2_1 CMD1 CMD0 PWM3 PWMB0 IOB2 IOB1 IOB0 Input port Output port Timer mode (input capture function) Complementary PWM mode waveform output...
Page 71 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Table 7.24 Port P2_4/TRDIOA1 Register TRDOER1 TRDFCR TRDIORA1 Function PD2_4 CMD1 CMD0 PWM3 IOA2 IOA1 IOA0 Input port Output port Timer mode (input capture function) Setting Complementary PWM mode waveform output value...
Page 72 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Table 7.27 Port P2_7/TRDIOD1 Register TRDOER1 TRDFCR TRDPMR TRDIORC1 Function PD2_7 CMD1 CMD0 PWM3 PWMD1 IOD2 IOD1 IOD0 Input port Output port Timer mode (input capture function) Complementary PWM mode waveform output...
Page 73 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Table 7.31 Port P3_4/SDA/SCS Register SSMR2 ICCR1 Function PD3_4 CSS1 CSS0 IICSEL Input port Output port Setting value SCS input SCS output SDA input/output X: 0 or 1 NOTES: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
Page 74 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Table 7.35 Port P4_3 Register Function PD4_3 Input port Setting value Output port NOTE: 1. Pulled up by setting the PU10 bit in the PUR0 register to 1. Table 7.36 Port P4_4...
Page 75 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Table 7.40 Port P6_0/TREO Register TRECR1 Function PD6_0 TOENA Input port Setting Output port value TREO output X: 0 or 1 NOTE: 1. Pulled up by setting the PU14 bit in the PUR0 register to 1.
Page 76 R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Table 7.46 Port P6_6/INT2/TXD1 Register U1MR U1C0 INTEN Function PD6_6 U1PINSEL SMD2 SMD1 SMD0 INT2EN Input port Output port INT2 input Setting value TXD1 output (CMOS output) TXD1 output (N-channel open-drain output)
Page 77: Unassigned Pin Handling
R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Unassigned Pin Handling Table 7.48 lists Unassigned Pin Handling. Table 7.48 Unassigned Pin Handling Pin Name Connection Ports P0 to P2, P3_0, • After setting to input mode, connect every pin to VSS via a resistor (pull- P3_1, P3_3 to P3_7, down) or connect every pin to VCC via a resistor (pull-up).
Page 78: Processor Mode
R8C/20 Group, R8C/21 Group 8. Processor Mode Processor Mode Processor Modes Single-chip mode can be selected as processor mode. Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1 Register. Table 8.1...
Page 79 9. Bus The bus cycles differ when accessing ROM/RAM, and when accessing SFR. Table 9.1 lists Bus Cycles by Access Space of the R8C/20 Group and Table 9.2 lists Bus Cycles by Access Space of the R8C/21 Group. The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word-(16 bits) unit, these area are accessed twice in 8-bit unit.
Page 80: Clock Generation Circuit
R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit 10. Clock Generation Circuit The clock generation circuit has: • XIN clock oscillation circuit • Low-speed on-chip oscillator • High-speed on-chip oscillator Table 10.1 lists Specifications of Clock Generation Circuit. Figure 10.1 shows a Clock Generation Circuit. Figures 10.2 to 10.7 show clock-associated registers.
Page 81 R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit FRA1 register Frequency adjustable High-speed FRA00 fOCO40M on-chip FRA2 register fOCO128 oscillator Divider (1/128) Watchdog Divider SSU/IIC timer fOCO-F FRA01 = 1 fOCO converter INT0 Timer RA Timer RB Timer RD Timer RE...
Page 82 R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit System Clock Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0006h 01101000b Bit Symbol Bit Name Function — Reserved bits Set to 0 (b1-b0) WAIT peripheral function clock stop...
Page 83 R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit System Clock Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0007h 00100000b Bit Symbol Bit Name Function (4,7,8) All clock stop control bit 0 : Oscillates clock...
Page 84 R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Oscillation Stop Detection Register b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 Symbol Address After Reset 000Ch 00000100b Bit Symbol Bit Name Function Oscillation stop detection enable 0 : Oscillation stop detection function...
Page 85 R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit High-Speed On-Chip Oscillator Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 Symbol Address After Reset 0023h FRA0 Bit Symbol Bit Name Function High-speed on-chip oscillator enable...
Page 86 R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit High-Speed On-Chip Oscillator Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 Symbol Address After Reset 0025h FRA2 Bit Symbol Bit Name Function High-speed on-chip oscillator...
Page 87: Xin Clock
R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit The following describes the clocks generated by the clock generation circuit. 10.1 XIN Clock This clock is supplied by a XIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks.
Page 88: On-Chip Oscillator Clocks
R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit 10.2 On-Chip Oscillator Clocks This clock is supplied by an on-chip oscillator. The on-chip oscillator contains a high-speed on-chip oscillator and a low-speed on-chip oscillator. Either an on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register.
Page 89: Cpu Clock And Peripheral Function Clock
R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit 10.3 CPU Clock and Peripheral Function Clock There are two type clocks: a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 10.1 Clock Generation Circuit.
Page 90: Power Control
R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit 10.4 Power Control There are three power control modes. All modes other than wait and stop modes are referred to as standard operating mode. 10.4.1 Standard Operating Mode Standard operating mode is further separated into three modes.
Page 91: Wait Mode
R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit 10.4.1.3 Low-Speed On-Chip Oscillator Mode If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) or the FRA01bit in the FRA0 register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillator clock.
Page 92 R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit 10.4.2.4 Exiting Wait Mode The MCU exits wait mode by a hardware reset or peripheral function interrupt. When using a hardware reset to exit wait mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to 000b (interrupts disabled) before executing the WAIT instruction.
Page 93 R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit FMR0 Register Time until Flash Memory is Time until CPU Clock is Time for Interrupt Remarks Activated (T1) Supplied (T2) Sequence (T3) FMSTP Bit Following total Period of system clock Period of CPU clock...
Page 94 R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit 10.4.2.5 Reducing Internal Power Consumption Internal power consumption can be reduced by using low-speed on-chip oscillator mode. Figure 10.10 shows the Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit. When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.10 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit.
Page 95: Stop Mode
R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit 10.4.3 Stop Mode Since the oscillator circuits stop in wait mode, the CPU clock and peripheral function clock stop and the CPU and peripheral functions clocked by these clocks stop operating. The least power required to operate the MCU is in stop mode.
Page 96 R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit FMR0 Register Time until Flash Memory is Time until CPU Clock is Time for Interrupt Remarks Activated (T2) Supplied (T3) Sequence (T4) FMSTP Bit Following total Period of system clock Period of CPU clock...
Page 97 R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Figure 10.12 shows the State Transitions in Power Control Mode. State Transition in Power Control Mode Reset Standard operating mode Low-speed on-chip oscillator mode CM14 = 0 OCD2 = 1 CM14 = 0...
Page 98: Oscillation Stop Detection Function
R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit 10.5 Oscillation Stop Detection Function The oscillation stop detection function is a function to detect the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register.
Page 99 R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Table 10.6 Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, and Voltage Monitor 2 Interrupts Generated Interrupt Source Bit Showing Interrupt Cause Oscillation Stop Detection (a) OCD3 bit in OCD register = 1...
Page 100 R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Interrupt sources judgment OCD3 = 1? (XIN clock stops) OCD1 = 1 (Oscillation stop detection interrupt enable), and OCD2=1 (Selects on-chip oscillator clock)? VW2C3 = 1? (Watchdog time underflows) OCD1 = 0 (Oscillation stop detection...
Page 101: Notes On Clock Generation Circuit
R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit 10.6 Notes on Clock Generation Circuit 10.6.1 Stop Mode When entering stop mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and the CM10 bit to “1” (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit in the CM1 register to “1”...
Page 102: Protection
R8C/20 Group, R8C/21 Group 11. Protection 11. Protection Protection function protects important registers from being easily overwritten when a program runs out of control. Figure 11.1 shows the PRCR Register. The following lists the registers protected by the PRCR register.
Page 103: Interrupts
R8C/20 Group, R8C/21 Group 12. Interrupts 12. Interrupts 12.1 Interrupt Overview 12.1.1 Types of Interrupts Figure 12.1 shows the Interrupts. Undefined instruction (UND instruction) Overflow (INTO instruction) Software BRK instruction (non-maskable interrupt) INT instruction Interrupt Watchdog timer Oscillation stop detection...
Page 104: Software Interrupts
R8C/20 Group, R8C/21 Group 12. Interrupts 12.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. The software interrupts are non-maskable interrupts. 12.1.2.1 Undefined Instruction Interrupt The undefined instruction interrupt is generated when the UND instruction is executed.
Page 105: Special Interrupts
R8C/20 Group, R8C/21 Group 12. Interrupts 12.1.3 Special Interrupts Special interrupts are non-maskable interrupts. 12.1.3.1 Watchdog Timer Interrupt The watchdog timer interrupt is generated by the watchdog timer. For details, refer to 13. Watchdog Timer. 12.1.3.2 Oscillation Stop Detection Interrupt Oscillation Stop Detection Interrupt is generated by the oscillation stop detection function.
Page 106: Interrupts And Interrupt Vector
R8C/20 Group, R8C/21 Group 12. Interrupts 12.1.5 Interrupts and Interrupt Vector There are 4 bytes in one vector. Set the starting address of interrupt routine in each vector table. When an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.
Page 107 R8C/20 Group, R8C/21 Group 12. Interrupts 12.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes from the starting address set in the INTB register. Table 12.2 lists the Relocatable Vector Tables. Table 12.2 Relocatable Vector Tables Software Interrupt Control...
Page 108: Interrupt Control
R8C/20 Group, R8C/21 Group 12. Interrupts 12.1.6 Interrupt Control The following describes enable/disable the maskable interrupts and set the priority order to acknowledge. The contents explained does not apply to the nonmaskable interrupts. Use the I flag in the FLG register, IPL and the ILVL2 to ILVL0 bits in each interrupt control register to enable/ disable the maskable interrupts.
Page 109 R8C/20 Group, R8C/21 Group 12. Interrupts Interrupt Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0048h XXXXX000b TRD0IC 0049h XXXXX000b TRD1IC SSUIC/IICIC 004Fh XXXXX000b Bit Symbol Bit Name Function Interrupt priority level select bits...
Page 110 R8C/20 Group, R8C/21 Group 12. Interrupts INTi Interrupt Control Register (i = 0 to 3) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0055h XX00X000b INT2IC 0059h XX00X000b INT1IC 005Ah XX00X000b INT3IC INT0IC 005Dh XX00X000b Bit Symbol...
Page 111 R8C/20 Group, R8C/21 Group 12. Interrupts 12.1.6.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (enabled) enables the maskable interrupt. Setting the I flag to 0 (disabled) disables all maskable interrupts.
Page 112 R8C/20 Group, R8C/21 Group 12. Interrupts 12.1.6.4 Interrupt Sequence An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine execution. When an interrupt request is generated while an instruction is executed, the CPU determines its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.
Page 113 R8C/20 Group, R8C/21 Group 12. Interrupts 12.1.6.5 Interrupt Response Time Figure 12.7 shows an Interrupt Response Time. The interrupt response time is the period between an interrupt request generation and the execution of the first instruction in an interrupt routine. An interrupt response time includes the period between an interrupt request generation and the completed execution of an instruction (refer to (a) in Figure 12.7) and the period required to perform an interrupt sequence (20 cycles, refer to (b) in...
Page 114 R8C/20 Group, R8C/21 Group 12. Interrupts 12.1.6.7 Saving a Register In the interrupt sequence, the FLG register and PC are saved to the stack. After 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG register, extended to 16 bits, are saved to the stack, the 16 low-order bits in the PC are saved.
Page 115 R8C/20 Group, R8C/21 Group 12. Interrupts 12.1.6.8 Returning from an Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved to the stack, are automatically returned. The program, executed before the interrupt request has been acknowledged, starts running again.
Page 116 R8C/20 Group, R8C/21 Group 12. Interrupts 12.1.6.10 Interrupt Priority Judgement Circuit The interrupt priority judgement circuit selects the highest priority interrupt. Figure 12.11 shows the Interrupt Priority Level Judgement Circuit. Priority level of each interrupt Highest Level 0 (default value)
Page 117: Int Interrupt
R8C/20 Group, R8C/21 Group 12. Interrupts 12.2 INT Interrupt 12.2.1 INTi Interrupt (i = 0 to 3) The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN register is set to 1 (enable). The edge polarity is selected using the INTiPL bit in the INTEN register and the POL bit in the INTiIC register.
Page 118 R8C/20 Group, R8C/21 Group 12. Interrupts _____ Input Filter Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00FAh INTF Bit Symbol Bit Name Function _____ b1 b0 INT0 input filter select bits 0 0 : No filter...
Page 119: Inti Input Filter (I = 0 To 3)
R8C/20 Group, R8C/21 Group 12. Interrupts 12.2.2 INTi Input Filter (i = 0 to 3) The INTi input contains a digital filter. The sampling clock is selected by the INTiF1 to INTiF0 bits in the INTF register. The IR bit in the INTiIC register is set to 1 (interrupt requested) when the INTi level is sampled for every sampling clock and the sampled input level matches three times.
Page 120: Key Input Interrupt
R8C/20 Group, R8C/21 Group 12. Interrupts 12.3 Key Input Interrupt A key input interrupt request is generated by one of the input edges of the K10 to K13 pins. The key input interrupt can be used as a key-on wake-up function to exit wait or stop mode.
Page 121 R8C/20 Group, R8C/21 Group 12. Interrupts Key Input Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00FBh KIEN Bit Symbol Bit Name Function KI0 input enable bit 0 : Disable KI0EN 1 : Enable...
Page 122: Address Match Interrupt
R8C/20 Group, R8C/21 Group 12. Interrupts 12.4 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register (i = 0 or 1). This interrupt is used for a break function of the debugger. When using the on-chip debugger, do not set an address match interrupt (the AIER, RMAD0 to RMAD1 registers, and relocatable vector tables) in a user system.
Page 123 R8C/20 Group, R8C/21 Group 12. Interrupts Address Match Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0013h AIER Bit Symbol Bit Name Function Address match interrupt 0 enable bit 0 : Disable AIER0...
Page 124 R8C/20 Group, R8C/21 Group 12. Interrupts 12.5 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts and I C bus Interface Interrupts (Interrupts with Multiple Interrupt Request Sources) Timer RD (channel 0), timer RD (channel 1), clock synchronous serial I/O with chip select and I...
Page 125 R8C/20 Group, R8C/21 Group 12. Interrupts Controlling an interrupt with the I flag, IR bit, ILVL0 to ILVL2 bits and IPL by Timer RD (channel 0), Timer RD (channel 1), clock synchronous serial I/O with chip select and I C bus interface is the same as that by other maskable interrupts.
Page 126: Notes On Interrupts
R8C/20 Group, R8C/21 Group 12. Interrupts 12.6 Notes on Interrupts 12.6.1 Reading Address 00000h Do not read the address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence.
Page 127: Changing Interrupt Sources
R8C/20 Group, R8C/21 Group 12. Interrupts 12.6.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
Page 128: Changing Interrupt Control Register Contents
R8C/20 Group, R8C/21 Group 12. Interrupts 12.6.5 Changing Interrupt Control Register Contents (a) Each interrupt control register can only be changed while interrupt requests corresponding to that register are not generated. If interrupt requests may be generated, disable the interrupts before changing the interrupt control register.
Page 129: Watchdog Timer
R8C/20 Group, R8C/21 Group 13. Watchdog Timer 13. Watchdog Timer The watchdog timer is a function to detect when the program is out of control. To use the watchdog timer is recommend for improving reliability of a system. The watchdog timer contains a 15-bit counter and can select count source protection mode is enabled or disabled.
Page 130 R8C/20 Group, R8C/21 Group 13. Watchdog Timer Option Function Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address Before Shipment 0FFFFh Bit Symbol Bit Name Function Watchdog timer start 0 : Starts w atchdog timer automatically after reset...
Page 131 R8C/20 Group, R8C/21 Group 13. Watchdog Timer Watchdog Timer Reset Register Symbol Address After Reset 000Dh Indeterminate WDTR Function When w riting 00h before w riting FFh, the w atchdog timer is reset. The default value of the w atchdog timer is set to 7FFFh w hen count source protection mode is disabled and 0FFFh w hen count source protection mode is enabled.
Page 132: Count Source Protection Mode Disabled
R8C/20 Group, R8C/21 Group 13. Watchdog Timer 13.1 Count Source Protection Mode Disabled The count source of the watchdog timer is the CPU clock when count source protection mode is disabled. Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled).
Page 133: Count Source Protection Mode Enabled
R8C/20 Group, R8C/21 Group 13. Watchdog Timer 13.2 Count Source Protection Mode Enabled The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. If the CPU clock stops when the program is out of control, the clock can be supplied to the watchdog timer.
Page 134: Timers
R8C/20 Group, R8C/21 Group 14. Timers 14. Timers The MCU contains two 8-bit timers with 8-bit prescaler, two 16-bit timers, and a timer with a 4-bit counter, and an 8- bit counter. The two 8-bit timers with the 8-bit prescaler contain timer RA and timer RB. These timers contain a reload register to memorize the default value of the counter.
Page 135 R8C/20 Group, R8C/21 Group 14. Timers Table 14.1 Functional Comparison of Timers Item Timer RA Timer RB Timer RD Timer RE Configuration 8-bit timer with 8-bit timer with 16-bit free-run timer X 2 4-bit counter 8-bit prescaler 8-bit prescaler (with input capture and...
Page 136: Timer Ra
R8C/20 Group, R8C/21 Group 14. Timers 14.1 Timer RA Timer RA is an 8-bit timer with an 8-bit prescaler. The prescaler and timer consist of the reload register and counter. The reload register and counter are allocated at the same address. When accessing the TRAPRE and TRA registers, the reload register and counter can be accessed (refer to Table 14.2 to 14.6 the Specification of Each Modes).
Page 137 R8C/20 Group, R8C/21 Group 14. Timers Timer RA Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0100h TRACR Bit Symbol Bit Name Function Timer RA count start bit 0 : Stops counting TSTART 1 : Starts counting...
Page 138 R8C/20 Group, R8C/21 Group 14. Timers Timer RA Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0102h TRAMR Bit Symbol Bit Name Function Timer RA operation mode b2 b1 b0 select bits 0 0 0 : Timer mode...
Page 139 R8C/20 Group, R8C/21 Group 14. Timers Timer RA Register Symbol Address After Reset 0104h Mode Function Setting Range Counts of an underflow of the TRAPRE All Modes 00h to FFh register NOTE: When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh.
Page 140: Timer Mode
R8C/20 Group, R8C/21 Group 14. Timers 14.1.1 Timer Mode In this mode, the timer counts an internally generated count source (see Table 14.2 Timer Mode Specifications). Figure 14.5 shows the TRAIOC Register in Timer Mode. Table 14.2 Timer Mode Specifications...
Page 141 R8C/20 Group, R8C/21 Group 14. Timers 14.1.1.1 Timer Write Control during Count Operation Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the reload register and counter.
Page 142: Pulse Output Mode
R8C/20 Group, R8C/21 Group 14. Timers 14.1.2 Pulse Output Mode Pulse output mode is mode to count the count source internally generated and outputs the pulse which inverts the polarity from the TRAIO pin each time the timer underflows (see Table 14.3 Pulse Output Mode Specifications).
Page 143 R8C/20 Group, R8C/21 Group 14. Timers Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0101h TRAIOC Bit Symbol Bit Name Function TRAIO polarity sw itch bit 0 : TRAIO output starts at “H”...
Page 144: Event Counter Mode
R8C/20 Group, R8C/21 Group 14. Timers 14.1.3 Event Counter Mode Event counter mode is mode to count an external signal which inputs from the INT1/TRAIO pin (see Table 14.4 Event Counter Mode Specifications). Figure 14.8 shows the TRAIOC Register in Event Counter Mode.
Page 145 R8C/20 Group, R8C/21 Group 14. Timers Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0101h TRAIOC Bit Symbol Bit Name Function TRAIO polarity sw itch bit 0 : Starts counting at rising edge of the TRAIO input or TRAIO starts output at “L”...
Page 146: Pulse Width Measurement Mode
R8C/20 Group, R8C/21 Group 14. Timers 14.1.4 Pulse Width Measurement Mode Pulse width measurement mode is mode to measure the pulse width of an external signal which inputs from the INT1/TRAIO pin (see Table 14.5 Pulse Width Measurement Mode Specifications).
Page 147 R8C/20 Group, R8C/21 Group 14. Timers Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0101h TRAIOC Bit Symbol Bit Name Function TRAIO polarity sw itch bit 0 : TRAIO input starts at “L”...
Page 148 R8C/20 Group, R8C/21 Group 14. Timers n = high-level: the contents of TRA register, low-level: the contents of TRAPRE register FFFFh Count start Underflow Count stop Count stop Count start Count start 0000h Period Set to 1 by program TSTART bit in...
Page 149: Pulse Period Measurement Mode
R8C/20 Group, R8C/21 Group 14. Timers 14.1.5 Pulse Period Measurement Mode Pulse period measurement mode is mode to measure the pulse period of an external signal which inputs from the INT1/TRAIO pin (see Table 14.6 Pulse Period Measurement Mode Specifications).
Page 150 R8C/20 Group, R8C/21 Group 14. Timers Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0101h TRAIOC Bit Symbol Bit Name Function TRAIO polarity sw itch bit 0 : Measures measurement pulse from one rising...
Page 151 R8C/20 Group, R8C/21 Group 14. Timers Underflow signal of timer RA prescaler Set to 1 by program TSTART bit in TRACR register Starts counting Measurement pulse (TRAIO pin input) TRA reloads TRA reloads Contents of TRA 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh...
Page 152: Notes On Timer Ra
R8C/20 Group, R8C/21 Group 14. Timers 14.1.6 Notes on Timer RA • Timer RA stops counting after reset. Set the value to timer RA and timer RA prescaler before the count starts. • Even if the prescaler and timer RA is read out in 16-bit units, these registers are read by 1 byte in the MCU.
Page 153: Timer Rb
R8C/20 Group, R8C/21 Group 14. Timers 14.2 Timer RB Timer RB is an 8-bit timer with an 8-bit prescaler. The prescaler and timer consist of the reload register and counter. (Refer to Table 14.7 to 14.10 the Specification of Each Modes).
Page 154 R8C/20 Group, R8C/21 Group 14. Timers Timer RB Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0108h TRBCR Bit Symbol Bit Name Function Timer RB count start bit 0 : Stops counting TSTART 1 : Starts counting...
Page 155 R8C/20 Group, R8C/21 Group 14. Timers Timer RB I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 010Ah TRBIOC Bit Symbol Bit Name Function Timer RB output level select Function varies depending on operating mode...
Page 156 R8C/20 Group, R8C/21 Group 14. Timers Timer RB Prescaler Register Symbol Address After Reset 010Ch TRBPRE Mode Function Setting Range Counts an internal count source or a timer RA Timer mode 00h to FFh underflow Programmable w aveform 00h to FFh...
Page 157: Timer Mode
R8C/20 Group, R8C/21 Group 14. Timers 14.2.1 Timer Mode Timer mode is mode to count a count source which is internally generated or timer RA underflow (see Table 14.7 Timer Mode Specifications). The TRBOCR and TRBSC registers are unused in timer mode.
Page 158 R8C/20 Group, R8C/21 Group 14. Timers 14.2.1.1 Timer Write Control during Count Operation Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to select whether writing to the prescaler or timer during count operation is performed to both the reload register and counter or only to the reload register.
Page 159 R8C/20 Group, R8C/21 Group 14. Timers When the TWRC bit is set to 0 (write to reload register and counter) Set 01h to the TRBPRE register and 25h to the TRBPR register by a program. Count source After writing, the reload register is written with the first count source.
Page 160: Programmable Waveform Generation Mode
R8C/20 Group, R8C/21 Group 14. Timers 14.2.2 Programmable Waveform Generation Mode Programmable waveform generation mode is mode to invert the signal output from the TRBO pin each time the counter underflows, while the values in the TRBPR and TRBSC registers are counted alternately (see Table 14.8 Programmable Waveform Generation Mode Specifications).
Page 161 R8C/20 Group, R8C/21 Group 14. Timers Timer RB I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 010Ah TRBIOC Bit Symbol Bit Name Function Timer RB output level select 0 : Outputs “H” for primary period Outputs “L”...
Page 162 R8C/20 Group, R8C/21 Group 14. Timers Set to 1 by program TSTART bit in TRBCR register Count source Timer RB prescaler underflow signal Timer RB secondary reloads Timer RB primary reloads Counter of timer RB Set to 0 when interrupt...
Page 163: Programmable One-Shot Generation Mode
R8C/20 Group, R8C/21 Group 14. Timers 14.2.3 Programmable One-shot Generation Mode Programmable one-shot generation mode is mode to output the one-shot pulse from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (see Table 14.9 Programmable One-Shot Generation Mode Specifications).
Page 164 R8C/20 Group, R8C/21 Group 14. Timers Timer RB I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 010Ah TRBIOC Bit Symbol Bit Name Function Timer RB output level select 0 : Outputs one-shot pulse “H”...
Page 165 R8C/20 Group, R8C/21 Group 14. Timers Set to 1 by program TSTART bit in TRBCR register Set to 0 when Set to 1 by INT0 pin Set to 1 by program counting ends input trigger TOSSTF bit in TRBOCR register...
Page 166 R8C/20 Group, R8C/21 Group 14. Timers 14.2.3.1 One-Shot Trigger Selection In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts).
Page 167: Programmable Wait One-Shot Generation Mode
R8C/20 Group, R8C/21 Group 14. Timers 14.2.4 Programmable Wait One-shot Generation Mode Programmable wait one-shot generation mode is mode to output the one-shot pulse from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (see Table 14.10 Programmable Wait One-Shot Generation Mode Specifications).
Page 168 R8C/20 Group, R8C/21 Group 14. Timers Table 14.10 Programmable Wait One-Shot Generation Mode Specifications Item Specification Count Sources f1, f2, f8, timer RA underflow Count Operations • Decrement the setting value in timer RB primary • When a count of timer RB primary underflows, the timer reloads the contents of the timer RB secondary before the count continues.
Page 169 R8C/20 Group, R8C/21 Group 14. Timers Timer RB I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 010Ah TRBIOC Bit Symbol Bit Name Function Timer RB output level select 0 : Outputs one-shot pulse “H”...
Page 170 R8C/20 Group, R8C/21 Group 14. Timers Set to 1 by program TSTART bit in TRBCR register Set to 1 by setting 1 to TOSST bit in TRBOCR Set to 0 when register, or INT0 pin input trigger counting ends TOSSTF bit in TRBOCR...
Page 171: Notes On Timer Rb
R8C/20 Group, R8C/21 Group 14. Timers 14.2.5 Notes on Timer RB • Timer RB stops counting after reset. Set the value to timer RB and timer RB prescaler before the count starts. • Even if the prescaler and timer RB is read out in 16-bit units, these registers are read by 1 byte in the MCU.
Page 172 R8C/20 Group, R8C/21 Group 14. Timers 14.2.5.2 Programmable waveform generation mode The following three workarounds should be performed in programmable waveform generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: •...
Page 173 R8C/20 Group, R8C/21 Group 14. Timers • Workaround example (b): As shown in Figure 14.26 detect the start of the primary period by the TRBO pin output level and write to registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
Page 174 R8C/20 Group, R8C/21 Group 14. Timers 14.2.5.4 Programmable wait one-shot generation mode The following three workarounds should be performed in programmable wait one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: •...
Page 175: Timer Rd
R8C/20 Group, R8C/21 Group 14. Timers 14.3 Timer RD Timer RD has 2 16-bit timers (channels 0 and 1). Each channel has 4 I/O pins. The operation clock of Timer RD is f1 or fOCO40M. Table 14.11 lists the Timer RD Operation Clocks.
Page 176 R8C/20 Group, R8C/21 Group 14. Timers Table 14.12 Pin Functions TRDIOA0/TRDCLK(P2_0) Register TRDOER1 TRDFCR TRDIORA0 Function PWM3 STCLK CMD1, CMD0 IOA3 IOA2_IOA0 XXXb PWM3 mode waveform output 001b, 01 X b Timer mode waveform output (output compare function) Setting 1XXb...
Page 177 R8C/20 Group, R8C/21 Group 14. Timers Table 14.15 Pin Functions TRDIOD0(P2_3) Register TRDOER1 TRDFCR TRDPMR TRDIORC0 Function PWM3 CMD1, CMD0 PWMD0 IOD2_IOD0 1 X b XXXb Complementary PWM mode waveform output XXXb Reset synchronous PWM mode waveform output XXXb PWM mode waveform output...
Page 178 R8C/20 Group, R8C/21 Group 14. Timers Table 14.18 Pin Functions TRDIOC1(P2_6) Register TRDOER1 TRDFCR TRDPMR TRDIORC1 Function PWM3 CMD1, CMD0 PWMC1 IOC2_IOC0 1 X b XXXb Complementary PWM mode waveform output XXXb Reset synchronous PWM mode waveform output XXXb PWM mode waveform output...
Page 179 R8C/20 Group, R8C/21 Group 14. Timers f1, f2, f4, f8, f32, fOCO40M Channel i TRDi register TRDGRAi register TRDGRBi register INT0 Count source TRDGRCi register TRDIOA0/TRDCLK select circuit TRDGRDi register TRDIOB0 TRDDFi register Timer RD control TRDIOC0 circuit TRDCRi register...
Page 180: Count Source
R8C/20 Group, R8C/21 Group 14. Timers 14.3.1 Count Source The count source selection can be used in all modes. However, in PWM3 mode, the external clock cannot be selected. Table 14.21 Count Source Selection Count Source Selection f1, f2, f4, f8, f32 The count source is selected by bits TCK2 to TCK0 in the TRDCRi register.
Page 181: Buffer Operation
R8C/20 Group, R8C/21 Group 14. Timers 14.3.2 Buffer Operation The TRDGRCi register can be used as the buffer register of the TRDGRAi register, and the TRDGRDi register can be used as the buffer register of the TRDGRBi register by the BFCi and BFDi bits in the TRDMR register.
Page 182 R8C/20 Group, R8C/21 Group 14. Timers Compare match signal TRDGRCi TRDGRAi register Comparator TRDi register (buffer) TRDi register TRDGRAi register Transfer TRDGRCi register (buffer) TRDIOAi output i = 0 or 1 The above applies to the following conditions: • BFCi bit in the TRDMR register is set to 1. (The TRDGRCi register is used as the buffer register of the TRDGRAi register.)
Page 183: Synchronous Operation
R8C/20 Group, R8C/21 Group 14. Timers 14.3.3 Synchronous Operation The TRD1 register is synchronized with the TRD0 register. • Synchronous preset When the SYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both the TRD0 and TRD1 registers after writing to the TRDi register.
Page 184: Pulse Output Forced Cutoff
R8C/20 Group, R8C/21 Group 14. Timers 14.3.4 Pulse Output Forced Cutoff In the output compare function, PWM mode, reset synchronous PWM mode, complementary PWM mode and PWM3 mode, the TRDIOji output pin can be forcibly set to the programmable I/O port by the INT0 pin input, and pulse output can be cut off.
Page 185 R8C/20 Group, R8C/21 Group 14. Timers EA0 bit EA0 bit writing value INT0 input Timer RD TRDIOA0 output data Port P2_0 PTO bit output data Port P2_0 input data EB0 bit EB0 bit writing value Timer RD TRDIOB0 output data...
Page 186: Input Capture Function
R8C/20 Group, R8C/21 Group 14. Timers 14.3.5 Input Capture Function The input capture function is to measure the external signal width and period. The content in the TRDi register (counter) is transferred to the TRDGRji register as a trigger of the TRDIOji (i = 0 or 1, j = either A, B, C or D) pin external signal (input capture).
Page 187 R8C/20 Group, R8C/21 Group 14. Timers Table 14.23 Input Capture Function Specifications Item Specification Count Sources f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) Count Operations Increment Count Period When the CCLR2 to CCLR0 bits in the TRDCRi register are set to 000b (free-running operation).
Page 188 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Start Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0137h 11111100b TRDSTR Bit Symbol Bit Name Function TRD0 count start flag 0 : Count stops TSTART0 1 : Count starts...
Page 189 R8C/20 Group, R8C/21 Group 14. Timers Timer RD PWM Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Symbol Address After Reset 0139h 10001000b TRDPMR Bit Symbol Bit Name Function PWM mode of TRDIOB0 selection bit...
Page 190 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Function Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 013Ah 10000000b TRDFCR Bit Symbol Bit Name Function Combination mode selection bit Set to 00b (timer mode, PWM mode, or CMD0 PWM3 mode) in the input capture function.
Page 191 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Digital Filter Function Selection Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 013Eh TRDDF0 013Fh TRDDF1 Bit Symbol Bit Name Function...
Page 192 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Control Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0140h TRDCR0 0150h TRDCR1 Bit Symbol Bit Name Function Count source selection bit...
Page 193 R8C/20 Group, R8C/21 Group 14. Timers Timer RD I/O Control Register Ai (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0141h 10001000b TRDIORA0 0151h 10001000b TRDIORA1 Bit Symbol Bit Name Function...
Page 194 R8C/20 Group, R8C/21 Group 14. Timers Timer RD I/O Control Register Ci (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0142h 10001000b TRDIORC0 0152h 10001000b TRDIORC1 Bit Symbol Bit Name Function...
Page 195 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Status Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0143h 11100000b TRDSR0 0153h 11000000b TRDSR1 Bit Symbol Bit Name Function Input capture/compare match flag [Source for setting this bit to 0] Write 0 after read.
Page 196 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Interrupt Enable Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0144h 11100000b TRDIER0 0154h 11100000b TRDIER1 Bit Symbol Bit Name Function...
Page 197 R8C/20 Group, R8C/21 Group 14. Timers Timer RD General Register Ai, Bi, Ci and Di (i = 0 or 1) (b15) (b8) Symbol Address After Reset 0149h-0148h FFFFh TRDGRA0 014Bh-014Ah FFFFh TRDGRB0 014Dh-014Ch FFFFh TRDGRC0 014Fh-014Eh FFFFh TRDGRD0 0159h-0158h FFFFh...
Page 198 R8C/20 Group, R8C/21 Group 14. Timers TRDCLK input count source Count value in TRDi register FFFFh 0009h 0006h 0000h TSTARTi bit in TRDSTR register 65536 TRDIOAi input TRDGRAi register 0006h 0009h Transfer Transfer TRDGRCi register 0006h IMFA bit in TRDSRi register...
Page 199 R8C/20 Group, R8C/21 Group 14. Timers 14.3.5.1 Digital Filter The TRDIOji input is sampled, and when the sampled input level matches 3 times, its level is assumed as a determination. Select the digital filter function and sampling clock by the TRDDFi register.
Page 200: Output Compare Function
R8C/20 Group, R8C/21 Group 14. Timers 14.3.6 Output Compare Function This function is to detect the match (compare match) of the content in the TRDGRji (j = either A, B, C and D) register with the content in the TRDi (i = 0 or 1) register. When the content matches, any level is output from the TRDIOji pin.
Page 201 R8C/20 Group, R8C/21 Group 14. Timers Table 14.25 Output Compare Function Specifications Item Specification Count Sources f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) Count Operations Increment Count Period •...
Page 202 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Start Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0137h 11111100b TRDSTR Bit Symbol Bit Name Function TRD0 count start flag 0 : Count stops TSTART0 1 : Count starts...
Page 203 R8C/20 Group, R8C/21 Group 14. Timers Timer RD PWM Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Symbol Address After Reset 0139h 10001000b TRDPMR Bit Symbol Bit Name Function PWM mode of TRDIOB0 selection bit...
Page 204 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Function Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 013Ah 10000000b TRDFCR Bit Symbol Bit Name Function Combination mode selection bit Set to 00b (timer mode, PWM mode, or...
Page 205 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Output Master Enable Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 013Bh TRDOER1 Bit Symbol Bit Name Function TRDIOA0 output disable bit 0 : Enable output 1 : Disable output (The TRDIOA0 pin is used as a programmable I/O port.)
Page 206 R8C/20 Group, R8C/21 Group 14. Timers (1,2) Timer RD Output Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 013Dh TRDOCR Bit Symbol Bit Name Function TRDIOA0 output level selection bit 0 : Initial output “L”...
Page 207 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Control Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0140h TRDCR0 0150h TRDCR1 Bit Symbol Bit Name Function Count source selection bit...
Page 208 R8C/20 Group, R8C/21 Group 14. Timers Timer RD I/O Control Register Ai (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0141h 10001000b TRDIORA0 0151h 10001000b TRDIORA1 Bit Symbol Bit Name Function...
Page 209 R8C/20 Group, R8C/21 Group 14. Timers Timer RD I/O Control Register Ci (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0142h 10001000b TRDIORC0 0152h 10001000b TRDIORC1 Bit Symbol Bit Name Function...
Page 210 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Status Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0143h 11100000b TRDSR0 0153h 11000000b TRDSR1 Bit Symbol Bit Name Function Input capture/compare match...
Page 211 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Interrupt Enable Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0144h 11100000b TRDIER0 0154h 11100000b TRDIER1 Bit Symbol Bit Name Function...
Page 212 R8C/20 Group, R8C/21 Group 14. Timers Timer RD General Register Ai, Bi, Ci and Di (i = 0 or 1) (b15) (b8) Symbol Address After Reset 0149h-0148h FFFFh TRDGRA0 014Bh-014Ah FFFFh TRDGRB0 014Dh-014Ch FFFFh TRDGRC0 014Fh-014Eh FFFFh TRDGRD0 0159h-0158h FFFFh...
Page 213 R8C/20 Group, R8C/21 Group 14. Timers Count source Value in TRDi register Count restarts Count stop TSTARTi bit in TRDSTR register m + 1 m + 1 Output level held TRDIOAi output Output inversed by compare match Initial output “L”...
Page 214 R8C/20 Group, R8C/21 Group 14. Timers 14.3.6.1 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi The TRDGRCi register can be used as output control of the TRDIOAi pin and the TRDGRDi register can be used as output control of the TRDIOBi pin. Therefore, each pin output can be controlled as follows: •...
Page 215 R8C/20 Group, R8C/21 Group 14. Timers Figure 14.62 lists the Operating Example When TRDGRCi Register is Used for Output Control of TRDIOAi Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin. Count source Value in TRDi register...
Page 216: Pwm Mode
R8C/20 Group, R8C/21 Group 14. Timers 14.3.7 PWM Mode PWM mode is to output a PWM waveform. Up to 3 PWM waveforms with the same period can be output by 1 channel. Also, Up to 6 PWM waveforms with the same period can be output by synchronizing Channels 0 and 1.
Page 217 R8C/20 Group, R8C/21 Group 14. Timers Table 14.27 PWM Mode Specifications Item Specification Count Sources f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) Count Operations Increment PWM Waveform PWM period: 1/fk x (m+1)
Page 218 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Start Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0137h 11111100b TRDSTR Bit Symbol Bit Name Function TRD0 count start flag 0 : Count stops TSTART0 1 : Count starts...
Page 219 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0138h 00001110b TRDMR Bit Symbol Bit Name Function Timer RD synchronous bit 0 : TRD0 and TRD1 registers operate...
Page 220 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Function Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 013Ah 10000000b TRDFCR Bit Symbol Bit Name Function Combination mode selection bit Set to 00b (timer mode, PWM mode, or CMD0 PWM3 mode) in PWM mode.
Page 221 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Output Master Enable Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 013Bh TRDOER1 Bit Symbol Bit Name Function TRDIOA0 output disable bit Set this bit to 1 (The TRDIOA0 pin is used as a programmable I/O mode) in PWM mode.
Page 222 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Output Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 013Dh TRDOCR Bit Symbol Bit Name Function TRDIOA0 output level selection bit Set this bit to 0 (enable...
Page 223 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Status Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0143h 11100000b TRDSR0 0153h 11000000b TRDSR1 Bit Symbol Bit Name Function Input capture/compare match...
Page 224 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Interrupt Enable Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0144h 11100000b TRDIER0 0154h 11100000b TRDIER1 Bit Symbol Bit Name Function...
Page 225 R8C/20 Group, R8C/21 Group 14. Timers Timer RD PWM Mode Output Level Control Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0145h 11111000b TRDPOCR0 0155h 11111000b TRDPOCR1 Bit Symbol...
Page 226 R8C/20 Group, R8C/21 Group 14. Timers Timer RD General Register Ai, Bi, Ci and Di (i = 0 or 1) (b15) (b8) Symbol Address After Reset 0149h-0148h FFFFh TRDGRA0 014Bh-014Ah FFFFh TRDGRB0 014Dh-014Ch FFFFh TRDGRC0 014Fh-014Eh FFFFh TRDGRD0 0159h-0158h FFFFh...
Page 227 R8C/20 Group, R8C/21 Group 14. Timers Count source Value in TRDi register m + 1 n + 1 m - n Active level “H” Inactive Level “L” TRDIOBi output p + 1 m - p Initial output “L” to compare match TRDIOCi output Inactive Level “H”...
Page 228 R8C/20 Group, R8C/21 Group 14. Timers Value in TRDi register 0000h TSTARTi bit in TRDSTR register Since the compare match in the TRDGRBi register is not generated, “L” is not applied to TRDIOBi output TRDIOBi output Duty 0 % TRDGRBi register p (p >...
Page 229: Reset Synchronous Pwm Mode
R8C/20 Group, R8C/21 Group 14. Timers 14.3.8 Reset Synchronous PWM Mode Output 3 normal-phases and 3 counter-phases of the PWM waveform with the same period (no three-phase, sawtooth wave modulation and dead time). Figure 14.76 shows the Block Diagram of Reset Synchronous PWM Mode, Table 14.29 lists the Reset Synchronous PWM Mode Specifications.
Page 230 R8C/20 Group, R8C/21 Group 14. Timers Table 14.29 Reset Synchronous PWM Mode Specifications Item Specification Count Sources f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) Count Operations The TRD0 register is incremented (The TRD1 register is not used.)
Page 231 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Start Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0137h 11111100b TRDSTR Bit Symbol Bit Name Function TRD0 count start flag 0 : Count stops TSTART0 1 : Count starts...
Page 232 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0138h 00001110b TRDMR Bit Symbol Bit Name Function Timer RD synchronous bit Set this bit to 0 (the TRD and TRD1 registers operate independently.) in reset synchronous...
Page 233 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Output Master Enable Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 013Bh TRDOER1 Bit Symbol Bit Name Function TRDIOA0 output disable bit Set this bit to 1 (the TRDIOA0 pin is used as a programmable I/O port) in reset synchronous PWM mode.
Page 234 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 Symbol Address After Reset 0140h TRDCR0 Bit Symbol Bit Name Function Count source selection bit b2 b1b0 0 0 0 : f1...
Page 235 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Status Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0143h 11100000b TRDSR0 0153h 11000000b TRDSR1 Bit Symbol Bit Name Function Input capture/compare match...
Page 236 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Interrupt Enable Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0144h 11100000b TRDIER0 0154h 11100000b TRDIER1 Bit Symbol Bit Name Function...
Page 237 R8C/20 Group, R8C/21 Group 14. Timers Timer RD General Register Ai, Bi, Ci and Di (i = 0 or 1) (b15) (b8) Symbol Address After Reset 0149h-0148h FFFFh TRDGRA0 014Bh-014Ah FFFFh TRDGRB0 014Dh-014Ch FFFFh TRDGRC0 014Fh-014Eh FFFFh TRDGRD0 0159h-0158h FFFFh...
Page 238 R8C/20 Group, R8C/21 Group 14. Timers Count source Value in TRD0 register 0000h TSTARTi bit in TRDSTR register m + 1 m - n TRDIOB0 output n + 1 TRDIOD0 output m - p TRDIOA1 output p + 1 TRDIOC1 output...
Page 239: Complementary Pwm Mode
R8C/20 Group, R8C/21 Group 14. Timers 14.3.9 Complementary PWM Mode Output 3 normal-phases and 3 counter-phases of the PWM waveform with the same period (with three-phase, triangular wave modulation and dead time). Figure 14.86 shows the Block Diagram of Complementary PWM Mode, Table 14.31 lists the Complementary PWM Mode Specifications.
Page 240 R8C/20 Group, R8C/21 Group 14. Timers Table 14.31 Complementary PWM Mode Specifications Item Specification Count Sources f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) Set the TCK2 to TCK0 bits in the TRDCR1 register to the same value (same count source) as the TCK2 to TCK0 bits in the TRDCR0 register.
Page 241 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Start Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0137h 11111100b TRDSTR Bit Symbol Bit Name Function TRD0 count start flag 0 : Count stops TSTART0 1 : Count starts...
Page 242 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0138h 00001110b TRDMR Bit Symbol Bit Name Function Timer RD synchronous bit Set this bit to 0 (The TRD0 and TRD1 registers operate independently.) in...
Page 243 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Function Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 013Ah 10000000b TRDFCR Bit Symbol Bit Name Function (1,2) Combination mode selection bit b1 b0 1 0 : Complementary PWM mode...
Page 244 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Output Master Enable Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 013Bh TRDOER1 Bit Symbol Bit Name Function TRDIOA0 output disable bit Set this bit to 1 (The TRDIOA0 pin is used as a programmable I/O port) in complementary PWM mode.
Page 245 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Control Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Symbol Address After Reset 0140h TRDCR0 0150h TRDCR1 Bit Symbol Bit Name Function...
Page 246 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Status Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0143h 11100000b TRDSR0 0153h 11000000b TRDSR1 Bit Symbol Bit Name Function Input capture/compare match flag A [Source for setting this bit to 0] Write 0 after read.
Page 247 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Interrupt Enable Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0144h 11100000b TRDIER0 0154h 11100000b TRDIER1 Bit Symbol Bit Name Function...
Page 248 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Counter 0 (b15) (b8) Symbol Address After Reset 0147h-0146h 0000h TRD0 Function Setting Range Set the dead time. Count a count source. Count operation is incremented or decremented. 0000h to FFFFh When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.
Page 249 R8C/20 Group, R8C/21 Group 14. Timers Table 14.32 TRDGRji Register Functions in Complementary PWM Mode Register Setting Register Function PWM Output Pin − TRDGRA0 General register. Set the PWM period at initialization. (Output inversed every Setting range: Setting value or above in TRD0 register...
Page 250 R8C/20 Group, R8C/21 Group 14. Timers Value in TRDi register Value in TRD0 register Value in TRDGRA0 register Value in TRD1 register Value in TRDGRB0 register Value in TRDGRA1 register Value in TRDGRB1 register 0000h TRDIOB0 output TRDIOD0 output TRDIOA1 output...
Page 251 R8C/20 Group, R8C/21 Group 14. Timers Count source Value in TRDi register m + 1 Value in TRD0 register Value in TRD1 register 0000h Set to FFFFh TSTART0 and TSTART1 bits in TRDSTR register TRDIOB0 output Initial output “H” Active level “L”...
Page 252 R8C/20 Group, R8C/21 Group 14. Timers 14.3.9.1 Transfer Timing from Buffer Register • Transfer from the TRDGRD0, TRDGRC1 and TRDGRD1 registers to the TRDGRB0, TRDGRA1 and TRDGRB1 registers When the CMD1 to CMD0 bits in the TRDFCR register are set to 10b, the content is transferred when the TRD1 register underflows.
Page 253: Pwm3 Mode
R8C/20 Group, R8C/21 Group 14. Timers 14.3.10 PWM3 Mode Output 2 PWM waveforms with the same period. Figure 14.98 shows the Block Diagram of PWM3 Mode, Table 14.33 lists the PWM3 Mode Specifications. Figures 14.99 to 14.107 show the Registers Associated with PWM3 Mode and Figure 14.108 shows the Operating Example of PWM3 Mode.
Page 254 R8C/20 Group, R8C/21 Group 14. Timers Table 14.33 PWM3 Mode Specifications Item Specification Count Sources f1, f2, f4, f8, f32, fOCO40M Count Operations The TRD0 register is incremented. (The TRD1 is not used.) PWM Waveform PWM period: 1/fk × (m + 1) Active level width of TRDIOA0 output: 1/fk ×...
Page 255 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Start Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0137h 11111100b TRDSTR Bit Symbol Bit Name Function TRD0 count start flag 0 : Count stops TSTART0 1 : Count starts...
Page 256 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0138h 00001110b TRDMR Bit Symbol Bit Name Function Timer RD synchronous bit This bit is disabled in PWM3 mode.
Page 257 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Output Master Enable Register 1 b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 Symbol Address After Reset 013Bh TRDOER1 Bit Symbol Bit Name Function TRDIOA0 output disable bit...
Page 258 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Output Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 013Dh TRDOCR Bit Symbol Bit Name Function TRDIOA0 output level 0 : Active level “H”, selection bit initial output “L”,...
Page 259 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Control Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 Symbol Address After Reset 0140h TRDCR0 Bit Symbol Bit Name Function Count source selection bit...
Page 260 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Status Register i (i = 0 or 1) b7 b6 b5 b4 b3 b1 b0 Symbol Address After Reset 0143h 11100000b TRDSR0 0153h 11000000b TRDSR1 Bit Symbol Bit Name Function Input capture/compare match flag A [Source for setting this bit to 0] Write 0 after read.
Page 261 R8C/20 Group, R8C/21 Group 14. Timers Timer RD Interrupt Enable Register i (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0144h 11100000b TRDIER0 0154h 11100000b TRDIER1 Bit Symbol Bit Name Function...
Page 262 R8C/20 Group, R8C/21 Group 14. Timers Timer RD General Register Ai, Bi, Ci and Di (i = 0 or 1) (b15) (b8) Symbol Address After Reset TRDGRA0 0149h-0148h FFFFh TRDGRB0 014Bh-014Ah FFFFh TRDGRC0 014Dh-014Ch FFFFh TRDGRD0 014Fh-014Eh FFFFh TRDGRA1 0159h-0158h...
Page 263 R8C/20 Group, R8C/21 Group 14. Timers Table 14.34 TRDGRji Register Functions in PWM3 Mode Register Setting Register Function PWM Output Pin TRDGRA0 − General register. Set the PWM period. TRDIOA0 Setting range: Value set in TRDGRA1 register or above TRDGRA1 General register.
Page 264 R8C/20 Group, R8C/21 Group 14. Timers Count source Value in TRD0 register FFFFh 0000h TSTART0 bit in TRDSTR register Count stop Set to 0 by a program CSEL0 bit in TRDSTR register m + 1 n + 1 m - n...
Page 265: Timer Rd Interrupt
R8C/20 Group, R8C/21 Group 14. Timers 14.3.11 Timer RD Interrupt Timer RD generates the Timer RD interrupt request based on 6 sources every channel. The Timer RD interrupt has 1 TRDiIC register (IR bit, ILVL0 to ILVL2 bits) every channel, and 1 vector.
Page 266 R8C/20 Group, R8C/21 Group 14. Timers Refer to TRDSR0 to TRDSR1 Registers in each mode (Figures 14.41, 14.56, 14.69, 14.81, 14.92 and 14.104) for the TRDSRi register. Refer to TRDIER0 to TRDIER1 Registers in each mode (Figures 14.42, 14.57, 14.70, 14.82, 14.93 and 14.105) for the TRDIERi register.
Page 267: Notes On Timer Rd
R8C/20 Group, R8C/21 Group 14. Timers 14.3.12 Notes on Timer RD 14.3.12.1 TRDSTR Register • Set the TRDSTR register using the MOV instruction. • When the CSELi (i = 0 or 1) is set to 0 (the count stops at compare match of registers TRDi and TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is written to the TSTARTi bit.
Page 268 R8C/20 Group, R8C/21 Group 14. Timers 14.3.12.4 Count Source Switch • When switching the count source, switch it after the count stops. Change procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops).
Page 269 R8C/20 Group, R8C/21 Group 14. Timers • When the value in the TRDGRA0 register is assumed as m, the TRD0 register counts order of m - 1, m, m + 1, m, m - 1 when changing from increment to decrement.
Page 270 R8C/20 Group, R8C/21 Group 14. Timers • The TRD1 register counts the order of 1, 0, FFFFh, 0, 1 when changing from decrement to increment. The UDF bit is set to 1 by the order of 1, 0, FFFFh operation. Also, when the CMD1 to CMD0 bits in the...
Page 271 R8C/20 Group, R8C/21 Group 14. Timers • Select with the CMD1 to CMD0 bits for the data transfer timing from the buffer register to the general register. However, transfer with the following timing in spite of the value of the CMD1 to CMD0 bits for the following cases: Value in buffer register ≥...
Page 272 R8C/20 Group, R8C/21 Group 14. Timers When the value in the buffer register is set to 0000h: Transfer by the compare match in the TRD0 and TRDGRA0 registers. And then, when setting the buffer register to 0001h or above and the smaller value than the one in the TRDGRA0 register, and the compare match in the TRD0 and TRDGRA0 registers in the fist time after setting, the value is transferred to the general register.
Page 273: Timer Re
R8C/20 Group, R8C/21 Group 14. Timers 14.4 Timer RE Timer RE has the 4-bit counter and 8-bit counter. Timer RE has the following mode: • Output compare mode Count a count source and detect the compare match The count source for timer RE is the operating clock that regulates the timing of timer operations.
Page 274: Output Compare Mode
R8C/20 Group, R8C/21 Group 14. Timers 14.4.1 Output Compare Mode The output compare mode is to count the internal count source divided-by-2 using the 4-bit or 8-bit counter and detect the compare value match with the 8-bit counter. Figure 14.114 shows the Block Diagram of Output Compare Mode and Table 14.37 lists the Output Compare Mode Specifications.
Page 275 R8C/20 Group, R8C/21 Group 14. Timers Table 14.37 Output Compare Mode Specifications Item Specification Count Source f4, f8, f32 Count Operation • Increment • When the 8-bit counter content matches with the TREMIN register content, the value returns to 00h and count continues.
Page 276 R8C/20 Group, R8C/21 Group 14. Timers Timer RE Counter Data Register Symbol Address After Reset 0118h TRESEC Function 8-bit counter data can be read. Although Timer RE stops counting, the count value is held. The TRESEC register is set to 00h w ith the compare match.
Page 277 R8C/20 Group, R8C/21 Group 14. Timers Timer RE Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 011Ch TRECR1 Bit Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. —...
Page 278 R8C/20 Group, R8C/21 Group 14. Timers Timer RE Count Source Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 011Eh TRECSR Bit Symbol Bit Name Function b1 b0 Count source select bit 0 0 : f4...
Page 279 R8C/20 Group, R8C/21 Group 14. Timers Count starts Matched Matched Matched TREMIN register setting value Time 1 by a program Set to TSTART bit in TRECR1 register 2 cycles of maximum count source TCSTF bit in 0 by acknowledgement of interrupt request...
Page 280: Notes On Timer Re
R8C/20 Group, R8C/21 Group 14. Timers 14.4.2 Notes on Timer RE 14.4.2.1 Starting and Stopping Count Timer RE has the TSTART bit for instructing count start or stop, and the TCSTF bit which indicates count start or stop. The TSTART and TCSTF bits are in the TRECR1 register.
Page 281: Serial Interface
R8C/20 Group, R8C/21 Group 15. Serial Interface 15. Serial Interface Serial Interface is configured with two channels: UART0 and UART1. Each UART0 and Uart1 has an exclusive timer to generate a transfer clock and they operate independently. Figure 15.1 shows the UARTi (i = 0 or 1) Block Diagram. Figure 15.2 shows the UARTi (i = 0 or 1) Transmit/Receive Unit.
Page 282 R8C/20 Group, R8C/21 Group 15. Serial Interface Clock synchronous type PRYE = 0 Clock UART (7 bits) synchronous disabled UART (7 bits) UARTi receive register UART (8 bits) type RXDi Clock UART UART (9 bits) enabled synchronous type PRYE = 1...
Page 283 R8C/20 Group, R8C/21 Group 15. Serial Interface (1,2) UARTi Transmit Buffer Register (i = 0 or 1) (b15) (b8) Symbol Address After Reset 00A3h-00A2h Indeterminate U0TB 00ABh-00AAh Indeterminate U1TB Bit Symbol Function — Transmit data (b8-b0) — Nothing is assigned. If necessary, set to 0.
Page 284 R8C/20 Group, R8C/21 Group 15. Serial Interface UARTi Transmit/Receive Mode Register (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset U0MR 00A0h U1MR 00A8h Bit Symbol Bit Name Function Serial I/O mode select bit...
Page 285 R8C/20 Group, R8C/21 Group 15. Serial Interface UARTi Transmit/Receive Control Register 0 (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00A4h 00001000b U0C0 00ACh 00001000b U1C0 Bit Symbol Bit Name Function...
Page 286 R8C/20 Group, R8C/21 Group 15. Serial Interface UART1 Function Select Register Symbol Address After Reset 00F5h Indeterminate U1SR Function Set to 03h w hen using UART1. As a result, UART1 can be used as the clock asynchronous serial I/O. Do not set values other than 03h.
Page 287: Clock Synchronous Serial I/O Mode
R8C/20 Group, R8C/21 Group 15. Serial Interface 15.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode is mode to transmit and receive data using a transfer clock. This mode is selected in UART0 only. Table 15.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers Used and Settings in Clock Synchronous Serial I/O Mode Table 15.1...
Page 288 R8C/20 Group, R8C/21 Group 15. Serial Interface Table 15.2 Registers Used and Settings in Clock Synchronous Serial I/O Mode Register Function U0TB 0 to 7 Set transmit data U0RB 0 to 7 Receive data can be read Overrun error flag...
Page 289 R8C/20 Group, R8C/21 Group 15. Serial Interface • Example of transmit timing (when internal clock is selected) Transfer clock TE bit in U0C1 register Set data in U0TB register TI bit in U0C1 register Transfer from U0TB register to UART0 transmit register...
Page 290: Polarity Select Function
R8C/20 Group, R8C/21 Group 15. Serial Interface 15.1.1 Polarity Select Function Figure 15.8 shows the Transfer Clock Polarity. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity. • When the CKPOL Bit in the U0C0 Register = 0 (output transmit data at the falling...
Page 291: Continuous Receive Mode
R8C/20 Group, R8C/21 Group 15. Serial Interface 15.1.3 Continuous Receive Mode Continuous receive mode is held by setting the U0RRM bit in the U0C1 register to 1 (enables continuous receive mode). In this mode, reading U0RB register sets the TI bit in the U0C1 register to 0 (data in the U0TB register).
Page 292: Clock Asynchronous Serial I/O (Uart) Mode
R8C/20 Group, R8C/21 Group 15. Serial Interface 15.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmit and receive data after setting the desired bit rate and transfer data format. Table 15.4 lists the UART Mode Specifications. Table 15.5 lists the Registers Used and Settings for UART Mode.
Page 293 R8C/20 Group, R8C/21 Group 15. Serial Interface Table 15.5 Registers Used and Settings for UART Mode Register Function UiTB 0 to 8 Set transmit data UiRB 0 to 8 (1, 2) Receive data can be read OER,FER,PER,SUM Error flag UiBRG...
Page 294 R8C/20 Group, R8C/21 Group 15. Serial Interface • Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit) Transfer clock TE bit in UiC1 register Write data to UiTB register TI bit in UiC1 register Transfer from UiTB register to UARTi transmit register...
Page 295 R8C/20 Group, R8C/21 Group 15. Serial Interface • Example of Receive Timing when Transfer Data is 8 Bits Long (parity disabled, one stop bit) UiBRG output UiC1 register RE bit Stop bit Start bit RXDi Determined “L” Receive data taken in...
Page 296: Bit Rate
R8C/20 Group, R8C/21 Group 15. Serial Interface 15.2.1 Bit Rate Divided-by-16 of frequency by the UiBRG (i = 0 or 1) register in UART mode is a bit rate. <UART Mode> • When selecting internal clock Setting value to the UiBRG register = Bit Rate ×...
Page 297: Notes On Serial Interface
R8C/20 Group, R8C/21 Group 15. Serial Interface 15.3 Notes on Serial Interface • When reading data from the UiRB (i = 0 or 1) register even in the clock asynchronous serial I/O mode or in the clock synchronous serial I/O mode. Ensure to read data in 16-bit unit. When the high-order byte of the UiRB register is read, the PER and FER bits in the UiRB register and the RI bit in the UiC1 register are set to 0.
Page 298: Clock Synchronous Serial Interface
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16. Clock Synchronous Serial Interface The clock synchronous serial interface is configured as follows. Clock Synchronous Serial Interface Clock synchronous serial I/O with chip select (SSU) Clock synchronous communication mode 4-wire bus communication mode...
Page 299: Clock Synchronous Serial I/O With Chip Select (Ssu)
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.2 Clock Synchronous Serial I/O with Chip Select (SSU) The serial data of the clock synchronous can communicate for the clock synchronous serial I/O with chip select. Table 16.2 lists the Clock Synchronous Serial I/O with Chip Select Specifications and Figure 16.1 shows a Block Diagram of Clock Synchronous Serial I/O with Chip Select.
Page 300 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Internal clock(f1/i) Internal clock generation circuit Multiplexer SSCK SSMR register SSCRL register SSCRH register Transmit/receive SSER register control circuit SSSR register SSMR2 register SSTDR register SSTRSR register Selector SSRDR register Interrupt requests...
Page 301 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface SS Control Register H b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00B8h SSCRH Bit Symbol Bit Name Function Transfer clock rate select bit b2 b1 b0...
Page 302 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface SS Control Register L b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00B9h 01111101b SSCRL Bit Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0.
Page 303 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface SS Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00BAh 00011000b SSMR Bit Symbol Bit Name Function Bit counter 2 to 0 b2 b1 b0...
Page 304 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface SS Enable Register b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 00BBh SSER Bit Symbol Bit Name Function Conflict error interrupt enable bit 0 : Disables conflict error interrupt request...
Page 305 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface SS Status Register b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 00BCh SSSR Bit Symbol Bit Name Function Conflict error flag 0 : No conflict error occurs 1 : Conflict error occurs —...
Page 306 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface SS Mode Register 2 b7 b6 b5 b4 b2 b1 Symbol Address After Reset 00BDh SSMR2 Bit Symbol Bit Name Function Clock synchronous serial I/O w ith 0 : Clock synchronous communication mode...
Page 307 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface SS Transmit Data Register Symbol Address After Reset 00BEh SSTDR Function Store the transmit data. The stored transmit data is transferred to the SSTRSR register and the transmit is started w hen detecting the SSTRSR register is empty.
Page 308: Transfer Clock
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.2.1 Transfer Clock A transfer clock can be selected from 7 internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8 and f1/4) and an external clock. When using the clock synchronous serial I/O with chip select, set the SCKS bit in the SSMR2 register to 1 and select the SSCK pin as the serial clock pin.
Page 309 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface • When SSUMS bit = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd edge) and CPOS bit = 0 (“H” when clock stops) SSCK SSO, SSI •...
Page 310: Ss Shift Register (Sstrsr)
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.2.2 SS Shift Register (SSTRSR) The SSTRSR register is the shift register to transmit and receive the serial data. When the transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to the bit 0 in the SSTRSR register.
Page 311: Interrupt Requests
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.2.3 Interrupt Requests Clock synchronous serial I/O with chip select has five interrupt requests: transmit data empty, transmit end, receive data full, overrun error and conflict error. Since these interrupt requests are assigned to the clock synchronous serial I/O with chip select interrupt vector table, determining interrupt sources by flags is required.
Page 312: Communication Modes And Pin Functions
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.2.4 Communication Modes and Pin Functions Clock synchronous serial I/O with chip select switches functions of the I/O pin in each communication mode according to the setting of the MSS bit in the SSCRH register and the RE and TE bits in the SSER register.
Page 313: Clock Synchronous Communication Mode
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.2.5 Clock Synchronous Communication Mode 16.2.5.1 Initialization in Clock Synchronous Communication Mode Figure 16.12 shows an Initialization in Clock Synchronous Communication Mode. Set the TE bit in the SSER register to 0 (disables transmit) and the RE bit to 0 (disables receive) before data transmit / receive as an initialization.
Page 314 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.2.5.2 Data Transmission Figure 16.13 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data Transmission (Clock Synchronous Communication Mode). During the data transmit, the clock synchronous serial I/O with chip select operates as described below.
Page 315 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Start Initialization (1) After reading the SSSR register and confirming Read TDRE bit in SSSR register that the TDRE bit is set to 1, write the transmit data to the SSTDR register. When write the transmit data to the SSTDR register, the TDRE bit is automatically set to 0.
Page 316 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.2.5.3 Data Reception Figure 16.15 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data Reception (Clock Synchronous Communication Mode). During the data receive, the clock synchronous serial I/O with chip select operates as described below. When the clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock and inputs data.
Page 317 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Start Initialization (1) After setting each register in the clock synchronous serial I/O with chip select register, dummy read on Dummy read on SSRDR register the SSRDR register is performed and receive operation is started.
Page 318 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.2.5.4 Data Transmission/Reception Data transmit/receive is a combined operation of data transmit and receive which are described before. Transmit/receive is started by writing data in the SSTDR register. When the 8th clock rises or the ORER bit is set to 1 (overrun error occurs) while the TDRE bit is set to 1 (data is transferred from the SSTDR to SSTRSR registers), the transmit/receive operation is stopped.
Page 319 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Start Initialization (1) After reading the SSSR register and confirming Read TDRE bit in SSSR register that the TDRE bit is set to 1, write the transmit data in the SSTDR register. When writing the transmit data to the SSTDR register, the TDRE bit is automatically set to 0.
Page 320: Operation In 4-Wire Bus Communication Mode
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.2.6 Operation in 4-Wire Bus Communication Mode 4-wire bus communication mode is a mode which communicates with the 4-wire bus; a clock line, data input line, data output line and chip select line. This mode includes bidirectional mode in which the data input line and data output line function as a single pin.
Page 321 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Start RE bit ← 0 SSER register TE bit ← 0 SSUMS bit ← 1 SSMR2 register (1) The MLS bit is set to 0 for MSB-first transfer. SSMR register Set bits CPHS and CPOS MLS bits ←...
Page 322 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.2.6.2 Data Transmission Figure 16.19 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data Transmission (4-Wire Bus Communication Mode). During the data transmit, the clock synchronous serial I/O with chip select operates as described below.
Page 323 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface • When CPHS bit = 0 (data change at even edges), CPOS bit = 0 (“H” when clock stops) High-impedance (Output) SSCK 1 frame 1 frame TDRE bit in SSSR register...
Page 324 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.2.6.3 Data Reception Figure 16.20 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data Reception (4-Wire Bus Communication Mode). During the data receive, the clock synchronous serial I/O with chip select operates as described below.
Page 325 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface • When CPHS bit = 0 (data download at even edges) and CPOS bit = 0 (“H” when clock stops) High-impedance (Output) SSCK 1 frame 1 frame RDRF bit in SSSR register...
Page 326: Scs Pin Control And Arbitration
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.2.7 SCS Pin Control and Arbitration When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode), and the CSS1 bit in the SSMR2 register to 1 (functions as SCS output pin), Set the MSS bit in the SSCRH register to 1 (operates as a master device) and check the arbitration of the SCS pin before starting serial transfer.
Page 327: Notes On Clock Synchronous Serial I/O With Chip Select
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use the clock synchronous serial I/O with chip select.
Page 328: I 2 C Bus Interface
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3 C Bus Interface The I C bus interface is the circuit which is used for a serial communication based on the data transfer format of the Philips I C bus.
Page 329 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Transfer clock generation circuit Output ICCR1 register control Transmit / receive ICCR2 register control circuit Noise rejection ICMR register circuit ICDRT register SAR register Output control ICDRS register Noise rejection Address comparison...
Page 330 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface SCL input SCL output SDA input SDA output (Master) SCL input SCL input SCL output SCL output SDA input SDA input SDA output SDA output (Slave 2) (Slave 1) Figure 16.23 External Circuit Connection Example of Pins SCL and SDA Rev.2.00 Aug 27, 2008...
Page 331 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface IIC Bus Control Register 1 b7 b6 b5 b4 b3 b2 Symbol Address After Reset 00B8h ICCR1 Bit Symbol Bit Name Function b3 b2 b1 b0 Transmit clock select bit 3 to...
Page 332 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface IIC Bus Control Register 2 b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 00B9h 01111101b ICCR2 Bit Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0.
Page 333 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface IIC Bus Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset ICMR 00BAh 00011000b Bit Symbol Bit Name Function Bit counter 2 to 0 C bus format (remaining transfer bit numbers...
Page 334 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface IIC Bus Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 00BBh ICIER Bit Symbol Bit Name Function Transmit acknow ledge 0 : 0 is transmitted as acknow ledge bit in receive...
Page 335 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface IIC Bus Status Register b7 b6 b5 b4 b2 b1 Symbol Address After Reset 00BCh 0000X000b ICSR Bit Symbol Bit Name Function General call address When detecting the general call address, this flag...
Page 336 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Slave Address Register b7 b6 b3 b2 Symbol Address After Reset 00BDh Bit Symbol Bit Name Function Format select bit 0 : I C bus format 1 : Clock synchronous serial format...
Page 337 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface IIC Bus Receive Data Register Symbol Address After Reset ICDRR 00BFh Function Store receive data When the ICDRS register receives 1-byte data, the receive data is transferred to the ICDRR register and the next receive is enabled.
Page 338: Transfer Clock
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3.1 Transfer Clock When the MST bit in the ICCR1 register is set to 0, the transfer clock is the external clock input from the SCL pin. When the MST bit in the ICCR1 register is set to 1, the transfer clock is the internal clock selected by the CKS0 to CKS3 bits in the ICCR1 register and the transfer clock is output from the SCL pin.
Page 339: Interrupt Requests
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3.2 Interrupt Requests The interrupt request of the I C bus interface contains 6 types when the I C bus format is used and 4 types when the clock synchronous serial format is used.
Page 340 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3.3 C Bus Interface Mode 16.3.3.1 C Bus Format Setting the FS bit in the SAR register to 0 communicates in I C bus format. Figure 16.32 shows the I C Bus Format and Bus Timing. The 1st frame following start condition consists of 8 bits.
Page 341 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3.3.2 Master Transmit Operation In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an acknowledge signal. Figure 16.33 and Figure 16.34 show the Operation Timing in Master Transmit Mode (I C Bus Interface Mode).
Page 342 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface (master output) (master output) Slave address (slave output) TDRE bit in ICSR register TEND bit in ICSR register ICDRT register Address + R/W Data 1 Data 2 Address + R/W Data 1...
Page 343 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3.3.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. Figure 16.35 and Figure 16.36 show the Operation Timing in Master Receive Mode (I C Bus Interface Mode).
Page 344 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Master transmit mode Master receive mode (master output) (master output) (slave output) TDRE bit in ICSR register TEND bit in ICSR register TRS bit in ICCR1 register RDRF bit in ICSR register...
Page 345 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface (master output) (master output) (slave output) RDRF bit in ICSR register RCVD bit in ICCR1 register Data n-1 ICDRS register Data n Data n-1 Data n ICDRR register (6) Stop condition...
Page 346 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3.3.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive clock and returns an acknowledge signal. Figure 16.37 and Figure 16.38 show the Operation Timing in Slave Transmit Mode (I C Bus Interface Mode).
Page 347 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Slave receive mode Slave transmit mode (master output) (master output) (slave output) (slave output) TDRE bit in ICSR register TEND bit in ICSR register TRS bit in ICCR1 register ICDRT register...
Page 348 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Slave receive mode Slave transmit mode (master output) (master output) (slave output) (slave output) TDRE bit in ICSR register TEND bit in ICSR register TRS bit in ICCR1 register Data n...
Page 349 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3.3.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an acknowledge signal. Figure 16.39 and Figure 16.40 show the Operation Timing in Slave Receive Mode (I C Bus Interface Mode).
Page 350 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface (master output) (master output) (slave output) (slave output) RDRF bit in ICSR register ICDRS register Data 1 Data 2 ICDRR register Data 1 Process (2) Dummy-read of ICDRR register (2) Read ICDRR register by program Figure 16.39...
Page 351: Clock Synchronous Serial Mode
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3.4 Clock Synchronous Serial Mode 16.3.4.1 Clock Synchronous Serial Format When setting the FS bit in the SAR register to 1, the clock synchronous serial format is used to communicate. Figure 16.41 shows the Transfer Format of Clock Synchronous Serial Format.
Page 352 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3.4.2 Transmit Operation In transmit mode, transmit data is output from the SDA pin synchronizing with the fall of the transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0.
Page 353 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3.4.3 Receive Operation In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0.
Page 354: Noise Canceller
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3.5 Noise Canceller The state of the SCL and SDA pins are routed through the noise rejection circuit before being latched internally. Figure 16.44 shows the Block Diagram of Noise Canceller.
Page 355: Bit Synchronization Circuit
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3.6 Bit Synchronization Circuit When setting the I C bus interface in master mode. • When the SCL signal is driven to “L” by the slave device. • Since the “H” period may become shorter while the SCL signal is driven to “L” by the slave device and the rising speed of the SCL signal is lowered by the load (load capacity and pull-up resistor) of the SCL line, the SCL signal is monitored and the communication synchronizes per bit.
Page 356: Examples Of Register Setting
R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3.7 Examples of Register Setting Figure 16.46 to Figure 16.49 show the Examples of Register Setting When Using I C Bus Interface. Start - Set the STOP bit in the ICSR register to 0.
Page 357 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Master receive mode TEND bit ← 0 ICSR register (1) Set the TEND bit to 0 and set to master receive mode. (1,2) Set the TDRE bit to 0 TRS bit ← 0...
Page 358 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Slave transmit mode (1) Set the AAS bit to 0 AAS bit ← 0 ICSR register (2) Set the transmit data (except the last byte) Write transmit data to ICDRT register...
Page 359 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Slave receive mode (1) Set the AAS bit to 0 AAS bit ← 0 ICSR register (2) Set the ACKBT bit to the transmit device ICIER register ACKBT bit ← 0...
Page 360 R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface 16.3.8 Notes on I C Bus Interface Set the IICSEL bit in the PMR register to 1 (select I C bus interface function) to use I C bus interface. 16.3.8.1 Multimaster Operation The following actions must be performed to use the I C bus interface in multimaster operation.
Page 361: Hardware Lin
R8C/20 Group, R8C/21 Group 17. Hardware LIN 17. Hardware LIN The hardware LIN performs LIN communication in cooperation with timer RA and UART0. 17.1 Features The hardware LIN has the following features. Figure 17.1 shows a Block Diagram of Hardware LIN.
Page 362: Input/Output Pins
R8C/20 Group, R8C/21 Group 17. Hardware LIN 17.2 Input/Output Pins Table 17.1 lists the Pin Configuration of the hardware LIN. Table 17.1 Pin Configuration Name Abbreviation Input/Output Function Receive Data Input RXD0 Input Receive data input pin of the hardware LIN...
Page 363: Register Configuration
R8C/20 Group, R8C/21 Group 17. Hardware LIN 17.3 Register Configuration The hardware LIN contains the following registers. • LIN Control Register (LINCR) • LIN Status Register (LINST) Figure 17.2 and Figure 17.3 show the LINCR and LINST Registers. LIN Control Register...
Page 364 R8C/20 Group, R8C/21 Group 17. Hardware LIN LIN Status Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0107h LINST Bit Symbol Bit Name Function Synch Field measurement- 1 show s Synch Field measurement completed. SFDCT...
Page 365: Functional Description
R8C/20 Group, R8C/21 Group 17. Hardware LIN 17.4 Functional Description 17.4.1 Master Mode Figure 17.4 shows a Typical Operation when Sending a Header Field. Figure 17.5 and Figure 17.6 show an Example of Header Field Transmission Flowchart. When transmitting a header field, the hardware LIN operates as described below.
Page 366 R8C/20 Group, R8C/21 Group 17. Hardware LIN Timer RA Set to timer mode TMOD0 to 2 bits in TRAMR register ← 000b Timer RA Set the pulse output level from low to start TEDGSEL bit in TRAIOC register ← 1...
Page 367 R8C/20 Group, R8C/21 Group 17. Hardware LIN Timer RA generates Synch Break. Timer RA Set the timer to start counting If the TRAPRE and TRA registers for TSTART bit in TRACR register ← 1 timer RA do not need to be read or...
Page 368: Slave Mode
R8C/20 Group, R8C/21 Group 17. Hardware LIN 17.4.2 Slave Mode Figure 17.7 shows a Typical Operation when Receiving a Header Field. Figure 17.8 through Figure 17.10 show an Example of Header Field Reception Flowchart. When receiving a header field, the hardware LIN operates as described below.
Page 369 R8C/20 Group, R8C/21 Group 17. Hardware LIN Timer RA Set to pulse width measurement mode Bits TMOD0 to TMOD2 in the TRAMR register ← 011b Timer RA Set the pulse width measurement level low TEDGSEL bit in the TRAIOC register ← 0 Timer RA Set the INT1/TRAIO pin to P1_5 TIOSEL bit in the TRAIOC register ←...
Page 370 R8C/20 Group, R8C/21 Group 17. Hardware LIN Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in the LINST register ← 1 Timer RA Set to start a pulse width measurement Timer RA waits until the timer TSTART bit in the TRACR register ←...
Page 371 R8C/20 Group, R8C/21 Group 17. Hardware LIN Hardware LIN measure the Synch Field. The interrupt of timer RA may be used. Hardware LIN Read the Synch Field measurement- (The SBDCT flag is set when the completed flag timer RA counter underflows upon SFDCT flag in the LINST register reaching the terminal count.)
Page 372: Bus Collision Detection Function
R8C/20 Group, R8C/21 Group 17. Hardware LIN 17.4.3 Bus Collision Detection Function The bus collision detection function can be used when UART0 is enabled for transmission (TE bit in the U0C1 register = 1). Figure 17.11 shows a Typical Operation when a Bus Collision is Detected.
Page 373: Hardware Lin End Processing
R8C/20 Group, R8C/21 Group 17. Hardware LIN 17.4.4 Hardware LIN End Processing Figure 17.12 shows an Example of Hardware LIN Communication Completion Flowchart. Use the following timing for hardware LIN end processing: • If the hardware bus collision detection function is used Perform hardware LIN end processing after checksum transmission completes.
Page 374: Interrupt Requests
R8C/20 Group, R8C/21 Group 17. Hardware LIN 17.5 Interrupt Requests There are four interrupt requests that are generated by the hardware LIN: Synch Break detection, Synch Break generation completed, Synch Field measurement, and bus collision detection. These interrupts are shared with the timer RA interrupt.
Page 375: Notes On Hardware Lin
R8C/20 Group, R8C/21 Group 17. Hardware LIN 17.6 Notes on Hardware LIN For the time-out processing of the header and response fields, use another timer to measure the duration of time with respect to a Synch Break detection interrupt as the starting point.
Page 376: A/D Converter
R8C/20 Group, R8C/21 Group 18. A/D Converter 18. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. The analog input shares the pins with P0_0 to P0_7, P1_0 to P1_3. Therefore, when using these pins, ensure the corresponding port direction bits are set to 0 (input mode).
Page 377 R8C/20 Group, R8C/21 Group 18. A/D Converter A/D conversion rate selection CKS0 = 1 fOCO-F CKS1 = 1 CKS0 = 0 CKS0 = 1 øAD CKS1 = 0 CKS0 = 0 VCUT = 0 AVSS Resistor ladder VCUT = 1...
Page 378 R8C/20 Group, R8C/21 Group 18. A/D Converter A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset ADCON0 00D6h Bit Symbol Bit Name Function Analog input pin select bit Refer to (4) A/D operation mode select...
Page 379 R8C/20 Group, R8C/21 Group 18. A/D Converter A/D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00D7h ADCON1 Bit Symbol Bit Name Function — Reserved bit Set to 0 (b2-b0) 8/10-bit mode select bit...
Page 380: One-Shot Mode
R8C/20 Group, R8C/21 Group 18. A/D Converter 18.1 One-Shot Mode In one-shot mode, the input voltage on one selected pin is A/D converted once. Table 18.2 lists the One-Shot Mode Specifications. Figure 18.4 shows the ADCON0 Register in One-Shot Mode and Figure 18.5 shows the ADCON1 Register in One-Shot Mode.
Page 381 R8C/20 Group, R8C/21 Group 18. A/D Converter A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset ADCON0 00D6h Bit Symbol Bit Name Function Analog input pin select bit Refer to (4) A/D operation mode select...
Page 382 R8C/20 Group, R8C/21 Group 18. A/D Converter A/D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 Symbol Address After Reset 00D7h ADCON1 Bit Symbol Bit Name Function — Reserved bit Set to 0 (b2-b0)
Page 383: Repeat Mode
R8C/20 Group, R8C/21 Group 18. A/D Converter 18.2 Repeat Mode In repeat mode, the input voltage on one selected pin is A/D converted repeatedly. Table 18.3 lists the Repeat Mode Specifications. Figure 18.6 shows the ADCON0 Register in Repeat Mode and Figure 18.7 shows the ADCON1 Register in Repeat Mode.
Page 384 R8C/20 Group, R8C/21 Group 18. A/D Converter A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset ADCON0 00D6h Bit Symbol Bit Name Function Analog input pin select bit Refer to (4) A/D operating mode select...
Page 385 R8C/20 Group, R8C/21 Group 18. A/D Converter A/D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 Symbol Address After Reset 00D7h ADCON1 Bit Symbol Bit Name Function — Reserved bit Set to 0 (b2-b0)
Page 386: Sample And Hold
R8C/20 Group, R8C/21 Group 18. A/D Converter 18.3 Sample and Hold When the SMP bit in the ADCON2 register is set to 1 (with sample and hold function), A/D conversion rate per pin increases. The sample and hold function is available in all operating modes. Start the A/D conversion after selecting whether the sample and hold circuit is to be used or not.
Page 387: A/D Conversion Cycles
R8C/20 Group, R8C/21 Group 18. A/D Converter 18.4 A/D Conversion Cycles Figure 18.9 shows the A/D Conversion Cycles. Conversion time at the 2nd Conversion time at the 1st bit End process bit and the follows Conversion Sampling Comparison Sampling Comparison...
Page 388: Internal Equivalent Circuit Of Analog Input
R8C/20 Group, R8C/21 Group 18. A/D Converter 18.5 Internal Equivalent Circuit of Analog Input Figure 18.10 shows the Internal Equivalent Circuit of Analog Input. VCC VSS AVCC ON Resistor Approx. 0.6k Ω Parasitic Diode ON Resistor Approx. 2k Ω Wiring Resistor C = Approx.1.5pF...
Page 389: Output Impedance Of Sensor Under A/D Conversion
R8C/20 Group, R8C/21 Group 18. A/D Converter 18.6 Output Impedance of Sensor Under A/D Conversion To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 18.11 has to be completed within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor equivalent circuit be R0, internal resistance of microcomputer be R, precision (error) of the A/D converter be X, and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).
Page 390: Notes On A/D Converter
R8C/20 Group, R8C/21 Group 18. A/D Converter 18.7 Notes on A/D Converter • Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit in the ADCON2 register when the A/D conversion stops (before a trigger occurs).
Page 391: Flash Memory
Rewrite control for block 0 by FMR16 bit and block 1 by FMR16 bit Number of Commands 5 commands Programming Blocks 0 and 1 R8C/20 Group: 100 times; R8C/21 Group: 1,000 times and erase (Program ROM) Blocks A and B 10,000 times...
Page 392 R8C/20 Group, R8C/21 Group 19. Flash Memory Table 19.2 Flash Memory Rewrite Modes Flash Memory CPU Rewrite Mode Standard Serial I/O Mode Parallel I/O Mode Rewrite Mode Function User ROM area is rewritten by User ROM area is rewritten User ROM area is...
Page 393: Memory Map
Memory Map The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 19.1 shows the Flash Memory Block Diagram for R8C/20 Group. Figure 19.2 shows the Flash Memory Block Diagram for R8C/21 Group. The user ROM area of R8C/21 Group contains an area which stores a MCU operating program (program ROM) and the 1-Kbyte block A and B (data flash).
Page 394 3. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on Emulator Debugger. 4. This area is to store the boot program provided by Renesas Technology. Figure 19.1 Flash Memory Block Diagram for R8C/20 Group Rev.2.00 Aug 27, 2008...
Page 395 3. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on Emulator Debugger. 4. This area is to store the boot program provided by Renesas Technology. Figure 19.2 Flash Memory Block Diagram for R8C/21 Group Rev.2.00 Aug 27, 2008...
Page 396: Functions To Prevent Rewriting Of Flash Memory
R8C/20 Group, R8C/21 Group 19. Flash Memory 19.3 Functions to Prevent Rewriting of Flash Memory Standard serial I/O mode contains an ID code check function, and the parallel I/O mode contains a ROM code protect function to prevent the flash memory from reading or rewriting easily.
Page 397: Rom Code Protect Function
R8C/20 Group, R8C/21 Group 19. Flash Memory 19.3.2 ROM Code Protect Function The ROM code protect function disables to read and change the internal flash memory by the OFS register in parallel I/O mode. Figure 19.4 shows the OFS Register.
Page 398: Cpu Rewrite Mode
R8C/20 Group, R8C/21 Group 19. Flash Memory 19.4 CPU Rewrite Mode In CPU rewrite mode, user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using such as a ROM programmer.
Page 399: Ew0 Mode
R8C/20 Group, R8C/21 Group 19. Flash Memory 19.4.1 EW0 Mode The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in the FMR0 register to 1 (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is set to 0, EW0 mode is selected.
Page 400 R8C/20 Group, R8C/21 Group 19. Flash Memory Figure 19.5 shows the FMR0 Register, Figure 19.6 shows the FMR1 Register and Figure 19.7 shows the FMR4 Register. 19.4.2.1 FMR00 Bit This bit indicates the operating status of the flash memory. The bit is 0 during programming, erasing (including suspend periods), or erase-suspend mode;...
Page 401 R8C/20 Group, R8C/21 Group 19. Flash Memory 19.4.2.11 FMR41 Bit In EW0 mode, the MCU enters erase-suspend mode when setting the FMR41 bit to 1 by a program. The FMR41 bit is automatically set to 1 (requests erase-suspend) when an interrupt request of an enabled interrupt is generated in EW1 mode, and then the MCU enters erase-suspend mode.
Page 402 R8C/20 Group, R8C/21 Group 19. Flash Memory Flash Memory Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 01B7h 00000001b FMR0 Bit Symbol Bit Name Function ____ 0 : Busy (During w riting or erasing)
Page 403 R8C/20 Group, R8C/21 Group 19. Flash Memory Flash Memory Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 01B5h 1000000Xb FMR1 Bit Symbol Bit Name Function — Reserved bit When read, its content is indeterminate.
Page 404 R8C/20 Group, R8C/21 Group 19. Flash Memory Flash Memory Control Register 4 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 01B3h 01000000b FMR4 Bit Symbol Bit Name Function Erase-suspend function 0 : Disable FMR40 enable bit...
Page 405 R8C/20 Group, R8C/21 Group 19. Flash Memory Figure 19.8 shows the Timing of Suspend Operation. Erase Erase Program Program Program Program Erase Erase starts suspends starts suspends restarts ends restarts ends During erase During erase During program During program Remains 0 during suspend...
Page 406 R8C/20 Group, R8C/21 Group 19. Flash Memory Figure 19.9 shows the How to Set and Exit EW0 Mode. Figure 19.10 shows the How to Set and Exit EW1 Mode. EW0 Mode Operating Procedure Rewrite control program Set the FMR01 bit by writing...
Page 407 R8C/20 Group, R8C/21 Group 19. Flash Memory High-speed on-chip oscillator mode, low-speed on-chip oscillator mode (XIN clock stops) program Transfer a high-speed on-chip oscillator mode, low- Write 0 to the FMR01 bit before writing speed on-chip oscillator mode (XIN clock stops)
Page 408: Software Commands
R8C/20 Group, R8C/21 Group 19. Flash Memory 19.4.3 Software Commands Software commands are described below. Read or write commands and data from or to in 8-bit units. Table 19.4 Software Commands First Bus Cycle Second Bus Cycle Command Data Data...
Page 409 R8C/20 Group, R8C/21 Group 19. Flash Memory 19.4.3.4 Program Command The program command writes data to the flash memory in 1-byte units. By writing 40h in the first bus cycle and data in the second bus cycle to the write address, and an auto program operation (data program and verify) will start.
Page 410 R8C/20 Group, R8C/21 Group 19. Flash Memory EW0 Mode Start Maskable interrupt FMR40 = 1 FMR44 = 1 ? Write the command code 40h to the write address FMR42 = 1 I = 1 (enable interrupt) FMR46 = 1 ?
Page 411 R8C/20 Group, R8C/21 Group 19. Flash Memory 19.4.3.5 Block Erase If writing 20h in the first bus cycle and D0h to the given address of a block in the second bus cycle, and an auto erase operation (erase and verify) will start.
Page 412 R8C/20 Group, R8C/21 Group 19. Flash Memory EW0 Mode Start Maskable interrupt FMR40 = 1 FMR43 = 1 ? Write the command code 20h FMR41 = 1 I = 1 (enable interrupt) FMR46 = 1 ? Write D0h to any block...
Page 413: Status Registers
R8C/20 Group, R8C/21 Group 19. Flash Memory 19.4.4 Status Registers The status register indicates the operating status of the flash memory and whether an erasing or programming operation completes normally or in error. Status of the status register can be read by the FMR00, FMR06, and FMR07 bits in the FMR0 register.
Page 414: Full Status Check
R8C/20 Group, R8C/21 Group 19. Flash Memory 19.4.5 Full Status Check When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to 1, indicating occurrence of each specific error. Therefore, checking these status bits (full status check) can determine the executed result.
Page 415 R8C/20 Group, R8C/21 Group 19. Flash Memory Command sequence error Full status check Execute the clear status register command (set these status flags to 0) FMR06 = 1 Command sequence error FMR07 = 1? Check if command is properly input...
Page 416: Standard Serial I/O Mode
R8C/20 Group, R8C/21 Group 19. Flash Memory 19.5 Standard Serial I/O Mode In standard serial I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a serial programmer which is applicable for the MCU.
Page 417 R8C/20 Group, R8C/21 Group 19. Flash Memory Table 19.8 Pin Functions (Flash Memory Standard Serial I/O Mode 3) Name Description VCC,VSS Power input Apply the voltage guaranteed for programming and erasure to the VCC pin and 0 V to the VSS pin.
Page 418 R8C/20 Group, R8C/21 Group 19. Flash Memory R8C/20 Group, R8C/21 Group MODE Connect oscillator circuit Package: PLQP0048KB-A NOTE: 1. No need to connect an oscillating circuit when operating with on-chip oscillator clock. Mode setting Signal Value Voltage from programmer MODE VSS →...
Page 419 R8C/20 Group, R8C/21 Group 19. Flash Memory 19.5.1.1 Example of Circuit Application in the Standard Serial I/O Mode Figure 19.18 shows an example of Pin Processing in Standard Serial I/O Mode 2 and Figure 19.19 shows an example of Pin Processing in Standard Serial I/O Mode 3. Since the controlled pins vary depending on the programmer, refer to the manual of your serial programmer.
Page 420: Parallel I/O Mode
R8C/20 Group, R8C/21 Group 19. Flash Memory 19.6 Parallel I/O Mode Parallel I/O mode is used to input and output the required software command, address and data parallel to controls (read, program and erase) for internal flash memory. Use a parallel programmer which supports this MCU. Contact the manufacturer of your parallel programmer about the parallel programmer and refer to the user’s manual of your...
Page 421: Notes On Flash Memory
R8C/20 Group, R8C/21 Group 19. Flash Memory 19.7 Notes on Flash Memory 19.7.1 CPU Rewrite Mode 19.7.1.1 Operating Speed Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register. This usage note is not needed for EW1 mode.
Page 422 R8C/20 Group, R8C/21 Group 19. Flash Memory Table 19.10 EW1 Mode Interrupts When Watchdog Timer, Oscillation When Maskable Interrupt Mode Status Stop Detection and Voltage Monitor 2 Request is Acknowledged Interrupt Request are Acknowledged EW1 During automatic erasing The auto-erasing is suspended...
Page 423 R8C/20 Group, R8C/21 Group 19. Flash Memory 19.7.1.7 Entering Stop Mode or Wait Mode Do not enter stop mode or wait mode during erase-suspend. Rev.2.00 Aug 27, 2008 Page 407 of 458 REJ09B0250-0200...
Page 424: Electrical Characteristics
R8C/20 Group, R8C/21 Group 20. Electrical Characteristics 20. Electrical Characteristics Table 20.1 Absolute Maximum Ratings Symbol Parameter Condition Rated value Unit Supply voltage -0.3 to 6.5 Input voltage -0.3 to V +0.3 Output voltage -0.3 to V +0.3 -40 ° C ≤ Topr ≤ 85 ° C Power dissipation 85 °...
Page 425 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Table 20.3 A/D Converter Characteristics Standard Symbol Parameter Conditions Unit Min. Typ. Max. − − − Resolution = AV Bits − φ − − Absolute 10-bit mode = 10 MHz, V = AV = 5.0 V...
Page 426 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied.
Page 427 6. If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at least three times until the erase error does not occur. 7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 8. 125 ° C for K version.
Page 428 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Suspend request (Maskable interrupt request) FMR46 Fixed time Clock-dependent time Access restart d(SR-SUS) Figure 20.2 Time delay until Suspend Table 20.6 Voltage Detection 1 Circuit Electrical Characteristics Standard Symbol Parameter Condition Unit Min.
Page 429 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Table 20.8 Power-on Reset Circuit, Voltage Monitor 1 Reset Circuit Electrical Characteristics Symbol Parameter Condition Standard Unit Min. Typ. Max. − − Power-on reset valid voltage por1 − Power-on reset or voltage monitor 1 valid voltage...
Page 430 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Table 20.9 High-Speed On-Chip Oscillator Circuit Electrical Characteristics Standard Symbol Parameter Condition Unit Min. Typ. Max. fOCO40M High-speed on-chip oscillator frequency temperature = 4.75 V to 5.25 V, 39.2 40.8 0 ° C ≤ Topr ≤ 60 ° C •...
Page 431 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Table 20.12 Timing Requirements of Clock Synchronous Serial I/O with Chip Select Standard Symbol Parameter Conditions Unit Min. Typ. Max. − − SSCK clock cycle time SUCYC − SSCK clock “H” width SUCYC −...
Page 432 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics 4-wire bus communication mode, Master, CPHS = 1 or V SCS (output) or V FALL RISE SSCK (output) (CPOS = 1) SSCK (output) (CPOS = 0) SUCYC SSO (output) SSI (input) 4-wire bus communication mode, Master, CPHS = 0...
Page 433 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics 4-wire bus communication mode, Slave, CPHS = 1 or V SCS (input) or V FALL RISE LEAD SSCK (input) (CPOS = 1) SSCK (input) (CPOS = 0) SUCYC SSO (input) SSI (output) 4-wire bus communication mode, Slave, CPHS = 0...
Page 434 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics or V SSCK or V SUCYC SSO (output) SSI (input) Figure 20.6 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode) Rev.2.00 Aug 27, 2008 Page 418 of 458...
Page 435 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Table 20.13 Timing Requirements of I C Bus Interface Standard Symbol Parameter Conditions Unit Min. Typ. Max. − − SCL input cycle time − − SCL input “H” width SCLH − − SCL input “L” width SCLL −...
Page 436 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Table 20.14 Electrical Characteristics (1) [V = 5 V] Standard Symbol Parameter Condition Unit Min. Typ. Max. − 2.0 − Output “H” Voltage Except XOUT = -5 mA = -200 µ A − 0.3 −...
Page 437 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Table 20.15 Electrical Characteristics (2) [V = 5 V] (Topr = -40 to 85°C (J version) / -40 to 125°C (K version), Unless Otherwise Specified.) Standard Symbol Parameter Condition Unit Min. Typ. Max.
Page 438 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Timing Requirements (Unless Otherwise Specified: V = 5 V, V = 0 V at Topr = 25°C) [V = 5 V] Table 20.16 XIN Input Standard Symbol Parameter Unit Min. Max. − XIN input cycle time c(XIN) −...
Page 439 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Table 20.18 Serial Interface Standard Symbol Parameter Unit Min. Max. − CLK0 input cycle time c(CK) − CLK0 input “H” width W(CKH) − CLK0 input “L” width W(CKL) − TXDi output delay time d(C-Q) −...
Page 440 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Table 20.20 Electrical Characteristics (3) [V = 3 V] Standard Symbol Parameter Condition Unit Min. Typ. Max. − 0.5 − Output “H” voltage Except XOUT = -1 mA − 0.5 − XOUT Drive capacity = -0.1 mA...
Page 441 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Table 20.21 Electrical Characteristics (4) [V = 3 V] (Topr = -40 to 85°C (J version) / -40 to 125°C (K version), Unless Otherwise Specified.) Standard Symbol Parameter Condition Unit Min. Typ. Max.
Page 442 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Timing Requirements (Unless Otherwise Specified: V = 3 V, V = 0V at Topr = 25°C) [V = 3 V] Table 20.22 XIN Input Standard Symbol Parameter Unit Min. Max. − XIN input cycle time c(XIN) −...
Page 443 R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Table 20.24 Serial Interface Standard Symbol Parameter Unit Min. Max. − CLK0 input cycle time c(CK) − CLK0 input “H” width W(CKH) − CLK0 input “L” width W(CKL) − TXDi output delay time d(C-Q) −...
Page 444: Usage Notes
R8C/20 Group, R8C/21 Group 21. Usage Notes 21. Usage Notes 21.1 Notes on Clock Generation Circuit 21.1.1 Stop Mode When entering stop mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and the CM10 bit to “1” (stop mode).
Page 445: Notes On Interrupts
R8C/20 Group, R8C/21 Group 21. Usage Notes 21.2 Notes on Interrupts 21.2.1 Reading Address 00000h Do not read the address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence.
Page 446: Changing Interrupt Sources
R8C/20 Group, R8C/21 Group 21. Usage Notes 21.2.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
Page 447: Changing Interrupt Control Register Contents
R8C/20 Group, R8C/21 Group 21. Usage Notes 21.2.5 Changing Interrupt Control Register Contents (a) Each interrupt control register can only be changed while interrupt requests corresponding to that register are not generated. If interrupt requests may be generated, disable the interrupts before changing the interrupt control register.
Page 448: Notes On Timers
R8C/20 Group, R8C/21 Group 21. Usage Notes 21.3 Notes on Timers 21.3.1 Notes on Timer RA • Timer RA stops counting after reset. Set the value to timer RA and timer RA prescaler before the count starts. • Even if the prescaler and timer RA is read out in 16-bit units, these registers are read by 1 byte in the MCU.
Page 449: Notes On Timer Rb
R8C/20 Group, R8C/21 Group 21. Usage Notes 21.3.2 Notes on Timer RB • Timer RB stops counting after reset. Set the value to timer RB and timer RB prescaler before the count starts. • Even if the prescaler and timer RB is read out in 16-bit units, these registers are read by 1 byte in the MCU.
Page 450 R8C/20 Group, R8C/21 Group 21. Usage Notes 21.3.2.2 Programmable waveform generation mode The following three workarounds should be performed in programmable waveform generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: •...
Page 451 R8C/20 Group, R8C/21 Group 21. Usage Notes • Workaround example (b): As shown in Figure 21.3 detect the start of the primary period by the TRBO pin output level and write to registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
Page 452 R8C/20 Group, R8C/21 Group 21. Usage Notes 21.3.2.4 Programmable wait one-shot generation mode The following three workarounds should be performed in programmable wait one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: •...
Page 453: Notes On Timer Rd
R8C/20 Group, R8C/21 Group 21. Usage Notes 21.3.3 Notes on Timer RD 21.3.3.1 TRDSTR Register • Set the TRDSTR register using the MOV instruction. • When the CSELi (i = 0 or 1) is set to 0 (the count stops at compare match of registers TRDi and TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is written to the TSTARTi bit.
Page 454 R8C/20 Group, R8C/21 Group 21. Usage Notes 21.3.3.4 Count Source Switch • When switching the count source, switch it after the count stops. Change procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops).
Page 455 R8C/20 Group, R8C/21 Group 21. Usage Notes • When the value in the TRDGRA0 register is assumed as m, the TRD0 register counts order of m - 1, m, m + 1, m, m - 1 when changing from increment to decrement.
Page 456 R8C/20 Group, R8C/21 Group 21. Usage Notes • The TRD1 register counts the order of 1, 0, FFFFh, 0, 1 when changing from decrement to increment. The UDF bit is set to 1 by the order of 1, 0, FFFFh operation. Also, when the CMD1 to CMD0 bits in the...
Page 457 R8C/20 Group, R8C/21 Group 21. Usage Notes • Select with the CMD1 to CMD0 bits for the data transfer timing from the buffer register to the general register. However, transfer with the following timing in spite of the value of the CMD1 to CMD0 bits for the following cases: Value in buffer register ≥...
Page 458 R8C/20 Group, R8C/21 Group 21. Usage Notes When the value in the buffer register is set to 0000h: Transfer by the compare match in the TRD0 and TRDGRA0 registers. And then, when setting the buffer register to 0001h or above and the smaller value than the one in the TRDGRA0 register, and the compare match in the TRD0 and TRDGRA0 registers in the fist time after setting, the value is transferred to the general register.
Page 459: Notes On Timer Re
R8C/20 Group, R8C/21 Group 21. Usage Notes 21.3.4 Notes on Timer RE 21.3.4.1 Starting and Stopping Count Timer RE has the TSTART bit for instructing count start or stop, and the TCSTF bit which indicates count start or stop. The TSTART and TCSTF bits are in the TRECR1 register.
Page 460: Notes On Serial Interface
R8C/20 Group, R8C/21 Group 21. Usage Notes 21.4 Notes on Serial Interface • When reading data from the UiRB (i = 0 or 1) register even in the clock asynchronous serial I/O mode or in the clock synchronous serial I/O mode. Ensure to read data in 16-bit unit. When the high-order byte of the UiRB register is read, the PER and FER bits in the UiRB register and the RI bit in the UiC1 register are set to 0.
Page 461: Clock Synchronous Serial Interface
R8C/20 Group, R8C/21 Group 21. Usage Notes 21.5 Clock Synchronous Serial Interface 21.5.1 Notes on Clock Synchronous Serial I/O with Chip Select Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use the clock synchronous serial I/O with chip select.
Page 462: Notes On Hardware Lin
R8C/20 Group, R8C/21 Group 21. Usage Notes 21.6 Notes on Hardware LIN For the time-out processing of the header and response fields, use another timer to measure the duration of time with respect to a Synch Break detection interrupt as the starting point.
Page 463: Notes On A/D Converter
R8C/20 Group, R8C/21 Group 21. Usage Notes 21.7 Notes on A/D Converter • Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit in the ADCON2 register when the A/D conversion stops (before a trigger occurs).
Page 464: Notes On Flash Memory
R8C/20 Group, R8C/21 Group 21. Usage Notes 21.8 Notes on Flash Memory 21.8.1 CPU Rewrite Mode 21.8.1.1 Operating Speed Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register. This usage note is not needed for EW1 mode.
Page 465 R8C/20 Group, R8C/21 Group 21. Usage Notes Table 21.3 EW1 Mode Interrupts When Watchdog Timer, Oscillation When Maskable Interrupt Mode Status Stop Detection and Voltage Monitor 2 Request is Acknowledged Interrupt Request are Acknowledged EW1 During automatic erasing The auto-erasing is suspended...
Page 466 R8C/20 Group, R8C/21 Group 21. Usage Notes 21.8.1.7 Entering Stop Mode or Wait Mode Do not enter stop mode or wait mode during erase-suspend. Rev.2.00 Aug 27, 2008 Page 450 of 458 REJ09B0250-0200...
Page 467: Notes On Noise
R8C/20 Group, R8C/21 Group 21. Usage Notes 21.9 Notes on Noise 21.9.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch-up Connect the bypass capacitor (at least 0.1 µF) using the shortest and thickest as possible.
Page 468: Notes On On-Chip Debugger
R8C/20 Group, R8C/21 Group 22. Notes on On-Chip Debugger 22. Notes on On-Chip Debugger When using the on-chip debugger to develop the R8C/20 and R8C/21 Groups program and debug, pay the following attention. Do not access the related UART1 registers.
Page 469: Notes On Emulator Debugger
23. Notes on Emulator Debugger 23. Notes on Emulator Debugger When using the emulator debugger to develop the R8C/20 and R8C/21 Groups program and debug, pay the following attention. Do not use the following flash memory areas because these areas are used for the emulator debugger.
Page 470: Appendix 1. Package Dimensions
R8C/20 Group, R8C/21 Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP48-7x7-0.50...
Page 471: Appendix 2. Connection Examples Between Serial Writer And On-Chip Debugging Emulator
R8C/20 Group, R8C/21 Group Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator Appendix Figure 2.1 shows the Connection Example with M16C Flash Starter (M3A-0806) and Appendix Figure 2.2 shows the Connection Example with E8 Emulator (R0E000080KCE00).
Page 472: Appendix 3. Example Of Oscillation Evaluation Circuit
R8C/20 Group, R8C/21 Group Appendix 3. Example of Oscillation Evaluation Circuit Appendix 3. Example of Oscillation Evaluation Circuit Appendix Figure 3.1 shows the Example of Oscillation Evaluation Circuit. RESET Connect oscillation circuit NOTE: 1. After reset, the XIN clock stops. Write a program to oscillate the XIN clock.
Page 473: Index
R8C/20 Group, R8C/21 Group Index Index [ A ] [ R ] AD ..................363 RMAD0 ................107 ADCON0 ............. 362, 365, 368 RMAD1 ................107 ADCON1 ............. 363, 366, 369 ADCON2 ................363 [ S ] ADIC ..................92 S0RIC ..................
Page 474 R8C/20 Group, R8C/21 Group Index TRECR2 ................261 TRECSR ................262 TREIC ................... 92 TREMIN ................260 TRESEC ................260 [ U ] U1SR ................... 270 UiBRG (i = 0 or 1) ..............267 UiC0 (i = 0 or 1) ..............269 UiC1 (i = 0 or 1) ..............
Page 475 “System Clock Generation” → “System clock generation circuit” revised Table 1.3 Product Information of R8C/20 Group revised. Figure 1.2 Type Number, Memory Size, and Package of R8C/20 Group revised. Table 1.4 Product Information of R8C/21 Group revised Figure 1.3 Type Number, Memory Size, and Package of R8C/21 Group revised.
Page 476 “2.8.8 Stack Pointer Select Flag (U Flag)” → “2.8.8 Stack Pointer Select Flag (U)” revised. 2.8.10 Reserved Bit “2.8.10 Reserved Area” → “2.8.10 Reserved Bit” revised. Figure 3.1 Memory Map of R8C/20 Group; “Internal ROM” → “Internal ROM (program ROM)” revised Address “1ZZZZh” added. NOTE revised.
Page 477 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 0.20 Jun 28, 2006 6.1 VCC Input Voltage; “6.1 Monitoring VCC Input Voltage” → “6.1 VCC Input Voltage” revised. Figure 7.2 Configuration of Programmable I/O Ports (2) revised.
Page 478 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 0.20 Jun 28, 2006 10.4.1.3 Low-Speed On-Chip Oscillator Mode, on the 8th line; “In this mode, ~ consumption operation.” added. 10.4.2.2 Entering Wait Mode revised. 10.4.2.3 Pin Status in Wait Mode revised.
Page 479 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 0.20 Jun 28, 2006 Table 14.8 Programmable Waveform Generation Mode Specifications, “Write to Timer” in the item; “TRAPRE” → “TRBPRE” corrected. Table 14.9 Programmable One-Shot Generation Mode Specifications, “Write to Timer”...
Page 480 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 0.20 Jun 28, 2006 14.3.5 Input Capture Function, on the 5th line; “The TRDGRA0 register ~ trigger input.” added. Figure 14.34 Block Diagram of Input Capture Function;...
Page 481 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 0.20 Jun 28, 2006 Figure 14.70 Registers TRDSR0 to TRDSR1 in PWM Mode revised. Table 14.29 Reset Synchronous PWM Mode Specifications revised. Figure 14.78 TRDSTR Register in Reset Synchronous PWM Mode revised.
Page 482 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 0.20 Jun 28, 2006 14.3.12 Notes on Timer RD; “14.3.13 Precautions on Timer RD” → “14.3.12 Notes on Timer RD” revised. 14.3.12.1 TRDSTR Register (i = 0 or 1) added.
Page 483 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 0.20 Jun 28, 2006 16.2.5.4 Data Transmission/Reception; “16.2.5.4 Data Transmit/Receive” → “16.2.5.4 Data Transmission/ Reception” revised. 16.2.5.4 Data Transmission/Reception, on the 5th line from the bottom; “When setting the ~ transmit is enabled.” deleted.
Page 484 19.2 Memory Map, on the 4th and 5th lines; “(program ROM)” and “(data flash)” added. Figure 19.1 Flash Memory Block Diagram for R8C/20 Group revised. Figure 19.2 Flash Memory Block Diagram for R8C/21 Group revised. 19.3 Functions to Prevent Rewriting of Flash Memory;...
Page 485 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 0.20 Jun 28, 2006 Figure 19.4 OFS Register revised. 19.4.2 EW1 Mode, on the 3rd line; “Do not execute software command ~” → “Do not execute command ~”...
Page 486 Table 1.3 Product Information for R8C/20 Group; “R5F2120AJFP (D)”, “R5F2120CJFP (D)”, “R5F2120AKFP (D)”, “R5F2120CKFP (D)”, and NOTE added. Figure 1.2 Type Number, Memory Size, and Package of R8C/20 Group; “A: 96 KB” and “C: 128 KB” added. Table 1.4 Product Information for R8C/21 Group;...
Page 487 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 1.00 Nov 15, 2006 Figure 5.4 OFS Register; NOTE2; “LVD0ON” → “LVD1ON” revised. 5.2 Power-On Reset Function NOTE1 deleted. NOTE2 revised. Figure 5.7 Example of Power-On Reset Circuit and Operation revised.
Page 488 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 1.00 Nov 15, 2006 10.4.1.3 Low-Speed On-Chip Oscillator Mode; On the 2nd line from the bottom; “To enter wait mode from low-speed clock mode, setting the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled) enables lower consumption current in wait mode.”...
Page 489 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 1.00 Nov 15, 2006 Figure 14.6 Registers TRAIOC and TRAMR in Timer Mode deleted. 14.1.1.1 Timer Write Control during Count Operation and Figure 14.6 Operating Example of Timer RA when Counter Value is Rewritten during Count Operation added.
Page 490 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 1.00 Nov 15, 2006 Table 14.7 Timer Mode Specifications; “Write to Timer” revised. Figure 14.21 Registers TRBIOC and TRBMR in Timer Mode → Figure 14.17 TRBIOC Register in Timer Mode replaced.
Page 491 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary Figure 14.35 Registers TRDSTR and TRDMR in Input Capture Function → 1.00 Nov 15, 2006 FIgure 14.32 Registers TRDSTR and TRDMR in Input Capture Function replaced. ; “TRD0 count start bit” → “TRD0 count start flag”...
Page 492 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 1.00 Nov 15, 2006 Table 14.31 Complementary PWM Mode Specifications, on the 3rd line from the bottom; “i = 0 to 2, j = either A, B, C or D” → “i = 0 or 1, j = either A, B, C or D” corrected.
Page 493 “When rewriting the block 2 and block 3 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to 1 (rewrite enables).” added. Figure 19.1 Flash Memory Block Diagram for R8C/20 Group revised. Figure 19.2 Flash Memory Block Diagram for R8C/21 Group revised.
Page 494 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 1.00 Nov 15, 2006 Table 19.8 Pin Functions (Flash Memory Standard Serial I/O Mode 3); P4_2/VREF deleted. P4_3 or P4_5 → P4_2 to P4_5 corrected. 19.7.1.7 Reset Flash Memory deleted.
Page 495 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 1.00 Nov 15, 2006 22. Notes on On-Chip Debugger, (2); “ROM 128 KB Product (R5F2120CJFP, R5F2120CKFP, R5F2121CJFP, R5F2121CKFP) addresses 23800h to 23FFFh” added. (3); ROM 128 KB Product (R5F2120CJFP, R5F2120CKFP, R5F2121CJFP, R5F2121CKFP) addresses 03B00h to 03BFFh added.
Page 496 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 1.10 Oct 31, 2007 Figure 13.2; • OFS register NOTE1 revised. • After Reset of WDC register: “000xxxxxb” → “00X11111b” Figure 14.6 Comment; “0 (During count)” → “1 (During count)”...
Page 497 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 1.10 Oct 31, 2007 Figure 16.25; NOTE5 deleted. Figure 16.26; NOTE3 revised and NOTE7 deleted. Figure 16.27; NOTE3 deleted. Figure 16.28; NOTE7 revised. Figure 16.32 revised. Figure 16.33 and Figure 16.34 revised.
Page 498 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 1.10 Oct 31, 2007 Figure 19.9; “any area other than the flash memory” → “the RAM” Figure 19.11; • “any area other than the flash memory” → “the RAM”...
Page 499 REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual Description Rev. Date Page Summary 2.00 Aug 27, 2008 172, 186, Figure 14.34, Figure 14.48, Figure 14.87, Figure 14.99; “0137Dh” → “0137h” 225, 239 Figure 14.62 revised Table 14.27 revised Figure 14.104 “Timer RD Status Register i (i = 0 or 1) ”...
Page 500 R8C/20 Group, R8C/21 Group Hardware Manual Publication Data: Rev.0.10 Sep 29, 2005 Rev.2.00 Aug 27, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan...
Page 501 R8C/20 Group, R8C/21 Group Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...

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