Sony SSC-DC593 Service Manual page 47

71
MCK
49
VCK/SCK
27
I4FSC
40
XCLR
64 - 65 10
DEFECT
D0 - D9
COMPENSATION
DEFECT
DETECTION
OPB
INTEGRATION
20
XV1
18
XSG1/SIN
3
PBLK
47
LID
SG
CBAR GEN.
53
TGHD
54
TGVD
65
CLPOB
44
HDO
SYNC GEN.
45
VDO
67
FLDO
18
SYNCO
31
FSCO
30
34
EXTSYNCI SCGATE
SYNC SEP.
23
35
EXTVDI PLLHV
22
33
EXTSCI PLLHVEN
PHASE COMP.
29
32
FSCI PLLSC
LB1940U-TLM-E (SANYO)
H BRIDGE MOTOR DRIVER
—TOP VIEW—
VS1 1 20 VC1
IN IN
SV 2 19 S-GND
CC OUT OUT
V 3 18 VC2
CC IN
OUT1 4 17 Vref
OUT OUT
RFG1 5 16 ENA1
OUT IN
OUT2 6 15 ENA2
OUT IN
OUT3 7 14 IN1
OUT IN
RFG2 8 13 IN2
OUT IN
OUT4 9 12 FC1
OUT OUT
VS2 10 11 FC2
IN OUT
INPUTS OUTPUTS
ENA IN OUT
SV
1 2 1 2 1 2 3 4
0 0 x x x x x x
1 x 0 1 x x
1 x
0 x 1 0 x x
x x x
1 0 1
x 1
x 0 x x 1 0
0 : LOW LEVEL
1 : HIGH LEVEL
x : DON'T CARE
SSC-DC593/DC593P/DC598P (E)
Y SIGNAL PROCESSOR
1H
VARIABLE
LPF
1HDL NR
CLP
H APERTURE CONT.
0+2H
1HDL + + V APERTURE CONT.
C SIGNAL PROCESSOR
LPF RGB
CLP MATRIX
OPDY
AE
DETECTOR
INPUTS
ENA1, ENA2 : CONTROL SIGNAL
IN1, IN2
VC1, VC2 : REFERENCE VOLTAGE FOR CONTROL
VS1, VS2 : POWER SUPPLY FOR MOTOR
OUTPUTS
FC1, FC2 : PHASE COMPENSATION CAPACITOR
CONNECTION TERMINAL
OUT1 - OUT4 : MOTOR DRIVE
RFG1, RFG2
: CONSTANT-CURRENT DETECTION
SV , S-GND : POWER SUPPLY OUTPUT FOR CONTROL
CC
SYSTEM
MODE
CC
OFF WAITING
ON 1ch REVERSE ROTATION
ON 1ch NORMAL ROTATION
ON 2ch REVERSE ROTATION
ON
2ch NORMAL ROTATION
γ
+
γ Y GAIN
HIGHLIGHT
+ APERTURE
ZOOM
CONT.
γ
HUE
x
GAIN
OPDC
AWB
DETECTOR
300Z
+
_
65k 80k
99 - 91
YI0 - YI7
90 - 84
YO0 - YO7
41
CHARM
42
8 8
CHARB
12
YDL DAC
YOUT
MEMORY
I/F
13
SFC ENC DAC
COUT
4 83 - 80
CI0 - CI3
69
MEMCID
4 79 - 77
CO0 - CO3
46
VGATE
38
XSCE
37 36
SI SIO SO
39
XSCK
V -SW
CC
REFERENCE VOLAGE
LOGIC CIRCUIT
65k 80k 65k 80k 65k 80k
IC
300Z
+
_
5-7