HP 16500B User Manual

Logic analysis system.
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User's Guide
Publication number 16500-97007
First Edition, February 1994
For Safety information, Warranties, and Regulatory
information, see the pages behind the index
© Copyright Hewlett-Packard Company 1987, 1990, 1993, 1994
All Rights Reserved
HP 16500B /16501A Logic
Analysis System

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  • Page 1

    User’s Guide Publication number 16500-97007 First Edition, February 1994 For Safety information, Warranties, and Regulatory information, see the pages behind the index © Copyright Hewlett-Packard Company 1987, 1990, 1993, 1994 All Rights Reserved HP 16500B /16501A Logic Analysis System...

  • Page 2

    A system of measurement modules A powerful, easy-to-use interface The touchscreen interface offers pop- The HP 16500B is the mainframe of the Hewlett-Packard Logic Analysis System. up menus and color graphics to lead It offers a modular structure for plug-in...

  • Page 3

    The HP 16501A is the add-on mainframe measurement features that allow you to for expanding the module capacity of capture complex system activity. the HP 16500B. When the two are Modules can connected, they form a single ten-card • be armed by an external instrument, system that is turned on and controlled by the HP 16500B.

  • Page 4

    Single card analyzers, oscilloscopes, Some measurement modules are and other options can go in any slot of sensitive to temperature and voltage the HP 16500B or HP 16501A. You should variations between different generally begin installing cards starting mainframes. Thus, when you install...

  • Page 5: Chapter 1, "triggering," Shows You How To Set Up The Analyzer To Trigger On The

    Triggering Intermodule Measurements File Management This User’s Guide shows you how to use the HP 16500B Logic Analysis System in your everyday debugging work. Concepts Chapter 1, “Triggering,” shows you how to set up the analyzer to trigger on the...

  • Page 6

    HP logic analyzer. See Also For general information on setup and operation of the HP 16500B, see the HP 16500B /16501A Logic Analysis System User’s Reference. For information on programming the HP 16500B using a computer controller such as a workstation or personal computer, see the HP 16500B/16501A Logic Analysis System Programmer’s Guide.

  • Page 7: Table Of Contents

    To start a group run of mod ules from an ex ter nal trig ger source 2–7 To start an ex ter nal in stru ment on com mand from a mod ule within the HP 16500 and 16501 main frame 2–9...

  • Page 8: Table Of Contents

    Us ing the HP 16500L LAN In ter face 3–13 To set up the HP 16500B 3–14 To trans fer data files from the HP 16500B sys tem to your com puter 3–16 To trans fer graph ics files from the HP 16500B sys tem to your com puter 3–18...

  • Page 9: Table Of Contents

    An event was n't cap tured by one of the mod ules 5–11 Mes sages 5–12 “De fault Cali bra tion Fac tors Loaded” (HP 16540, 16541, and 16542) 5–12 “. . . In verse As sem bler Not Found” 5–12 “Meas ure ment Ini tiali za tion Er ror”...

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    Contents “Wait ing for Trig ger” 5–15 6 Ap pli ca tion Notes...

  • Page 11

    Triggering...

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    Triggering As you begin to understand a problem in your system, you may realize that certain conditions must occur before the problem occurs. You can use sequential triggering to ensure that those conditions have occurred before the analyzer recognizes its trigger and captures information.

  • Page 13: To Store And Time The Execution Of A Subroutine

    Triggering To store and time the execution of a subroutine To store and time the execution of a subroutine Most systems software of any kind is composed of a hierarchy of functions and procedures. During integration, testing, and performance evaluation, you will want to look at specific procedures to verify that they are executing correctly and that the implementation is efficient.

  • Page 14

    Triggering To store and time the execution of a subroutine Trigger Setup for Storing Execution of a Subroutine For processors that do prefetching of instructions or have pipelined architectures, you may want to add part or all of the depth of the pipeline to the start address for In_Range1 to ensure that the analyzer does not trigger on a prefetched but unexecuted state.

  • Page 15: To Trigger On The Nth Iteration Of A Loop

    Triggering To trigger on the nth iteration of a loop To trigger on the nth iteration of a loop Traditional debugging requires print statements around the area of interest. This is not possible in most embedded systems designs. But, the analyzer allows you to view the system’s behavior when a particular event occurs.

  • Page 16

    Triggering To trigger on the nth iteration of a loop Trigger Setup for Triggering on the 10th Iteration of a Loop...

  • Page 17: To Trigger On The Nth Recursive Call Of A Recursive Function

    Triggering To trigger on the nth recursive call of a recursive function To trigger on the nth recursive call of a recursive function Select the state analyzer Trigger menu. Define the terms CALL_ADD, F_START, and F_END to represent the called address of the recursive function, and the start and end addresses of the function.

  • Page 18

    Triggering To trigger on the nth recursive call of a recursive function Triggering on the 22nd Call of a Recursive Function...

  • Page 19: To Trigger On Entry To A Function

    Triggering To trigger on entry to a function To trigger on entry to a function This sequence triggers on entry to a function only when it is called by one particular function. Select the state analyzer Trigger menu. Define the terms F1_START and F1_END to represent the start and end addresses of the calling function.

  • Page 20

    Triggering To trigger on entry to a function Triggering on Entry to a Function...

  • Page 21

    Triggering To capture a trace of activity associated with a write of know particular variable To capture a trace of activity associated with a write of known bad data to a particular variable The trigger specification ANDs the bad data on the data bus, write transaction on the status bus, and address of the variable on the address bus.

  • Page 22: To Trig Ger On A Loop That Oc Ca Sion Ally Runs Too Long

    Triggering To trigger on a loop that occasionally runs too long To trigger on a loop that occasionally runs too long This example assumes the loop normally executes in 14 µs. Select the state analyzer Trigger menu. Define terms LP_START, LP_END, and Timer1 to represent the start and end addresses of the loop, and the normal duration of the loop.

  • Page 23: To Ver Ify That All Stacks And Reg Is Ters Are Re Stored Cor Rectly Bef Ore Ex It Ing A Sub Rou Tine

    Triggering To verify that all stacks and registers are restored correctly be subroutine Triggering on a Loop Overrun To verify that all stacks and registers are restored correctly before exiting a subroutine The exit code for a function will often contain instructions for deallocating stack storage for local variables and restoring registers that were saved during the function call.

  • Page 24

    Triggering To verify that all stacks and registers are restored correctly before exiting a subroutine • Store “anystate” Verifying Correct Return from a Function Call Only three sequence terms are shown on the display at a time. You can scroll through the terms using the knob when the “State Sequence Levels”...

  • Page 25: To Trig Ger Af Ter All Status Bus Lines Fin Ish Tran Si Tion Ing

    Triggering To trigger after all status bus lines finish transitioning To trigger after all status bus lines finish transitioning In some applications, you will want to trigger a measurement when a particular pattern has become stable. For example, you might want to trigger the analyzer when a microprocessor’s status bus has become stable during the bus cycle.

  • Page 26

    Triggering To find the nth occurrence of asserting a chip select line To find the nth occurrence of asserting a chip select line Select the timing analyzer Trigger menu. Define the glitch/edge1 term to represent the asserting transition on the chip select line. You can rename the Edge1 term to make it correspond more closely to the problem domain, for example, to CHIP_SEL.

  • Page 27: To Ver Ify That The Chip Se Lect Line Of A Mem Ory Chip Is Strobed Af Ter The Ad Dress On The Ad Dress Bus Is Sta Ble

    Triggering To verify that the chip select line of a memory chip is strob on the address bus is stable To verify that the chip select line of a memory chip is strobed after the address on the address bus is stable Select the timing analyzer Trigger menu.

  • Page 28: To Trig Ger When Ex Pected Data Does Not Ap Pear On The Data Bus From A Re Mote De Vice When Re Quested

    Triggering To trigger when expected data does not appear on the data bus from a remote device when requested To trigger when expected data does not appear on the data bus from a remote device when requested Select the timing analyzer Trigger menu. Define a term called DATA to represent the expected data, the Edge1 term to represent the chip select line of the remote device, and the Timer1 term to identify the time limit for receiving expected data.

  • Page 29

    Triggering To trigger when expected data does not appear on the data b device when requested Triggering When I/O Data Not Returned...

  • Page 30: To Test Mini Mum And Maxi Mum Pulse Lim Its

    Triggering To test minimum and maximum pulse limits To test minimum and maximum pulse limits Select the timing analyzer Trigger menu. Define the Edge1 term to represent the positive-going transition, and define the Edge2 term to represent the negative-going transition on the line with the pulse to be tested.

  • Page 31

    Triggering To test minimum and maximum pulse limits Triggering when a Pulse Exceeds Minimum or Maximum Limits...

  • Page 32: To Detect A Handshake Violation

    Triggering To detect a handshake violation To detect a handshake violation Select the timing analyzer Trigger menu. Define the Edge1 term to represent either transition on the first handshake line, and the Edge2 term to represent either transition on the second handshake line. You can rename these terms to match your problem, for example, to REQ and ACK.

  • Page 33: To Detect Bu Contention

    Triggering To detect bus contention To detect bus contention In this sequencer setup, the trigger occurs only if both devices assert their bus transfer acknowledge lines at the same time. Select the timing analyzer Trigger menu. Define the Edge1 term to represent assertion of the bus transfer acknowledge line of one device, and Edge2 term to represent assertion of the bus transfer acknowledge line of the other device.

  • Page 34: Cross- Arming Trig Ger Ex Am Ples

    Cross-Arming Trigger Examples The following examples use cross arming to coordinate measurements between two instruments. The cross-arming is set up in the Arming Control menu (obtained by selecting Arming Control in the Trigger menu). When coordinating measurements between two or more analyzers, select Count Time so you can correlate the measurements made by the two analyzers.

  • Page 35: To Examine Software Execution When A Timing Violation Occur

    Triggering To examine software execution when a timing violation occu To examine software execution when a timing violation occurs The timing analyzer triggers when the timing violation occurs, and when it triggers, it also sets its “arm” level to true. When the state analyzer receives the arm signal, it triggers immediately on the present state.

  • Page 36: To Look At Con Trol And Status Sig Nals Dur Ing Exe Cu Tion Of A Rou Tine

    Triggering To look at control and status signals during execution of a routine To look at control and status signals during execution of a routine The state analyzer will trigger on the start of the routine whose control and status signals are to be examined with finer resolution than once per bus cycle.

  • Page 37

    Intermodule Measurements...

  • Page 38

    The figure on the opposite page shows how intermodule bus arming signals are connected between modules inside the HP 16500B and HP 16501A. Note that any arm input can be driven by any slot, and that the port input line can drive any slot.

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    Intermodule Measurements Intermodule Bus Block Functional Diagram...

  • Page 40

    Intermodule Measurement Examples To set up an intermodule measurement, you must use the Intermodule menu. All modules that will participate in the intermodule measurement must be represented in this menu and their relationships must be shown under the Group Run field.

  • Page 41: To Set Up A Group Run Of Mod Ules Within The Hp 16500b

    Intermodule Measurements To set up a group run of modules within the HP 16500B To set up a group run of modules within the HP 16500B Modules are armed in the configuration tree by either an individual module or the Group Run field. When armed, a module begins searching for the input that will satisfy its trigger specification.

  • Page 42

    Intermodule Measurements To set up a group run of modules within the HP 16500B The analyzer in slot B is armed when the oscilloscope in slot D finds its trigger condition. Oscilloscope Arms State Analyzer in Group Run...

  • Page 43: To Start A Group Run Of Mod Ules From An Ex Ter Nal Trig Ger Source

    To start a group run of modules from an external trigger source Connect the arm signal from the external instrument or system to the PORT IN BNC connector on the rear panel of the HP 16500 frame. Select the Intermodule menu. Set up the group run specification.

  • Page 44

    B and the oscilloscope in slot D are armed when the PORT IN signal arrives. State Analyzer and Oscilloscope armed from PORT IN See Also “To set up a group run of modules within the HP 16500B” in this chapter.

  • Page 45: To Start An Ex Ter Nal In Stru Ment On Com Mand From A Mod Ule Within The Hp 16500 And 16501 Main Frame

    The output from the PORT OUT BNC is an active high TTL level. See Also “To set up a group run of modules within the HP 16500B” or “To start a group run of modules from an external trigger source” in this chapter.

  • Page 46

    Intermodule Measurements To start an external instrument on command from a module within the HP 16500 and 16501 mainframe The analyzer in slot B drives port out after finding its trigger. Driving the Port Out BNC in an Intermodule Measurement...

  • Page 47: To See The Status Of A Mod Ule Within An In Ter Mod Ule Meas Ure Ment

    Intermodule Measurements To see the status of a module within an intermodule measure To see the status of a module within an intermodule measurement Select the Intermodule menu. Find the name of the module under the “Modules” list, and read the status under the module name.

  • Page 48

    Intermodule Measurements To see time correlation of each module within an intermodule measurement To see time correlation of each module within an intermodule measurement Time correlation in the intermodule menu can help you see when the trigger occurred for each module and the relative time range of data captured by that module.

  • Page 49: To Use A Timing Analyzer To Detect A Glitch

    You must have fully independent state and timing analyzers to make this type of measurement. For example, though the HP 16550A can be configured to use some of its channels for a state analyzer and some for a timing analyzer, it cannot present those analyzers independently for intermodule measurements.

  • Page 50: To Cap Ture The Wave Form Of A Glitch

    Intermodule Measurements To capture the waveform of a glitch To capture the waveform of a glitch The following setup uses the triggering capability of the timing analyzer and the acquisition capability of the oscilloscope. Select the Intermodule Menu. Select the timing analyzer from the Modules list and set it to Group Run.

  • Page 51

    Intermodule Measurements To capture state flow showing how your target system proces To capture state flow showing how your target system processes an interrupt Use an oscilloscope with a sample rate faster than the microprocessor clock rate to trigger on the asynchronous interrupt request. Select the Intermodule menu.

  • Page 52

    Intermodule Measurements To capture state flow showing how your target system processes an interrupt Interrupt Capture Setup...

  • Page 53: Us Ing Stimulus- Response To Test A Cir Cuit

    You can also use the pattern generators with the logic analyzer to test PC boards when no board-test system is available. The HP 16520A and HP 16521A pattern generators for the HP 16500B avoid the inconvenience of having to stack several signal generators on top of each other, with all of the cable connections required for those signal generators.

  • Page 54

    Intermodule Measurements Using stimulus-response to test a circuit Stimulus-Response Setup See Also The HP 16520A User’s Reference for the procedures for operating the pattern generator.

  • Page 55: To Use A State Ana Lyzer To Trig Ger Tim Ing Analy Sis Of A Count- Down On A Set Of Data Lines

    Intermodule Measurements To use a state analyzer to trigger timing analysis of a count-d data lines To use a state analyzer to trigger timing analysis of a count-down on a set of data lines Select the Intermodule menu. Select the state analyzer from the Modules list and set it to Group Run.

  • Page 56

    Intermodule Measurements To use two state analyzers to monitor the activity of coprocessors in a target system To use two state analyzers to monitor the activity of coprocessors in a target system Select the Intermodule menu. Select the first state analyzer from the Modules list and set it to Group Run.

  • Page 57: Spe Cial Dis Plays

    The Mixed Display mode allows you to show state listings and waveforms together on screen, if all were obtained by modules within the HP 16500B and 16501A frame. State listings are shown at the top of the screen and waveform displays are shown at the bottom. You can interleave state listings from two analyzers at the top of the screen, if desired.

  • Page 58: To In Ter Leave Trace Lists

    In the first case, you might have two HP 16550A analyzers configured in a group run; in the second, you might have a single HP 16550A configured as two state analyzers. The interleaved trace lists...

  • Page 59

    Interleaved states are shown in yellow with line numbers indented from those of the primary analyzer. Interleaved Trace Lists on the HP 16550A See Also “To set up a group run of modules within the HP 16500B” in this chapter.

  • Page 60: To View Trace Lists And Wave Forms To Gether On The Same Dis Play

    You won’t need to do this if the two measurement modules for which you want mixed display are really part of the same module. For example, you might have an HP 16550A state/timing analyzer configured as two separate analyzers, one a state analyzer, the other a timing analyzer. You can use mixed display to view the timing analyzer waveform with the trace lists from the state analyzer.

  • Page 61

    See Also X and O markers from the waveform display are shown in their relative position on the state display. “To set up a group run of modules within the HP 16500B” in this chapter. “Skew Adjustment” in this chapter.

  • Page 62: Skew Ad Just Ment

    Skew Adjustment You can modify the skew or timing deviation between modules within the intermodule measurement. This allows you to compensate for any known delay of the system under test, or to compare two signals by first removing any displayed skew between the signal channels. Skew adjustments can correct module delays to within 2 ns of other modules.

  • Page 63: To Ad Just For Mini Mum Skew Be Tween Two Mod Ules In Volved In An In Ter Mod Ule Meas Ure Ment

    Intermodule Measurements To adjust for minimum skew between two modules involve measurement To adjust for minimum skew between two modules involved in an intermodule measurement Connect an input signal from each module to the same signal. An ideal signal for testing skew is a single-shot signal with fast risetime. Such a signal simplifies triggering and makes it easier to correlate the input event between the modules.

  • Page 64

    Intermodule Measurements To adjust for minimum skew between two modules involved in an intermodule measurement Record the difference between waveform events shown by the two modules. You can use the X and O markers to measure the differences in delays. Select the Intermodule Menu.

  • Page 65

    File Management...

  • Page 66

    File Management A host computer such as a PC or UNIX workstation can enhance the HP 16500B in many ways. You can use the host to store configuration files or measurement results for later review. Screen images from the HP 16500B can be saved in bitmap files for inclusion in reports developed using word processors or desktop publishing tools.

  • Page 67: Trans Fer Ring Files Us Ing The Flexi Ble Disk Drive

    Transferring Files Using the Flexible Disk Drive Because the flexible disk drive on the HP 16500B will read and write double-sided, double density or high-density disks in MS-DOS format, it is a useful tool for transferring images to and from IBM PC- compatible computers as well as other systems that can read and write MS-DOS format.

  • Page 68: To Save A Meas Ure Ment Con Figu Ra Tion

    File Management To save a measurement configuration To save a measurement configuration You can save measurement configurations on a 3.5" disk or on the internal hard disk for later use. This is especially useful for automating repetitive measurements for production testing. Select System from the module field.

  • Page 69

    File Management To save a measurement configuration If you want to save your file in a directory other than the root, you can select Change Directory from the disk operations field. Then type the name of the desired directory in the directory name field, or select it from the list of visible directories using the knob.

  • Page 70: To Load A Meas Ure Ment Con Figu Ra Tion

    Also, configurations are slot dependent. If you save a configuration for a particular module, rearrange the modules within the HP 16500B, then try to reload the configuration, the configuration will not load.

  • Page 71

    File Management To load a measurement configuration Loading Configuration for all HP 16500B Modules and the System...

  • Page 72

    To save a trace list in ASCII format To save a trace list in ASCII format Some HP 16500B displays, such as file lists and trace lists, contain columns of ASCII data that you may want to move to a PC for further manipulation or analysis.

  • Page 73

    File Management To save a trace list in ASCII format 68332EVS State Listing Label ADDR CPU32 Mnemonic STAT __________ _____ ______________________________________ _________________ 406F4 ANDI.L #********,(A6)+ Opcode Fetch 0FF7A 0004 data write Data Write 0FF7C 06F6 data write Data Write 40992 BSR.B 0004093E Opcode Fetch...

  • Page 74

    File Management To save a menu or measurement as a graphic image To save a menu or measurement as a graphic image You can save menus and measurements to disk in one of four different graphics formats. Insert a DOS-formatted flexible disk in the flexible disk drive. Set up the menu whose image you want to capture, or run a measurement from which you want to save data.

  • Page 75

    File Management To save a menu or measurement as a graphic image An Oscilloscope Display Saved as a TIF Image...

  • Page 76: To Load Sys Tem Soft Ware

    Repeat steps 7 and 8 for all files you need to update. If you have more than one disk from which you want to copy files, turn the knob after changing disks. This ensures that the HP 16500B will read the directory on the new disk.

  • Page 77: Us Ing The Hp 16500l Lan In Ter Face

    Logic Analysis System by making it look like a NFS (Network File System) node. Using NFS utilities for the PC or NFS on a UNIX workstation, you can transfer files to and from the HP 16500B as if it were a disk drive attached to your machine. The LAN Interface also...

  • Page 78

    To set up the HP 16500B To set up the HP 16500B You can set up the HP 16500B from the front panel, or via the LAN. To set up the system via the LAN, you can use one of three methods: •...

  • Page 79

    HP 16500B into an HP 16550A state/timing module. The HP 16550A is installed in slot B of the HP 16500B mainframe. To load the configuration file from the HP 16500B hard disk, you need to send the programming command to the analyzer.

  • Page 80: To Trans Fer Data Files From The Hp 16500b Sys Tem To Your Com Puter

    To transfer data files from the HP 16500B system to your computer You can transfer data from the HP 16500B system to your PC or workstation by copying files. Data files in binary format are available in file locations \slot_x\data.raw. These binary files can be transferred to your computer and then reloaded into the HP 16500B system later.

  • Page 81

    Example You have an HP 16550A state/timing analyzer installed in slot C of your HP 16500B mainframe. The name of analyzer 1 of the HP 16550A is 68000_BUS. You have created some labels under analyzer 1 of the HP 16550A, including one called “addr_lo.” The directory structure of the...

  • Page 82

    The file screenbw.epi is a black and white Encapsulated PostScript file in EPS version 3.0 format. You can also save the current display to a file on one of the local HP 16500B disk drives, using the Print to Disk function. You can then transfer the file from the HP 16500B drive to your computer.

  • Page 83

    Concepts...

  • Page 84

    Concepts Understanding how the analyzer does its job will help you use it more effectively and minimize measurement problems. This chapter explains the general operation of the trigger sequencer and the inverse assembler.

  • Page 85: The Trig Ger Se Quencer

    There are several different logic analyzers available for the HP 16500B. This discussion will focus on the HP 16550A, a 100-MHz state/500-MHz timing analyzer. Most HP logic analyzers will be similar, differing only in the number of available states, pattern resources, range resources, and acquisition memory depth.

  • Page 86

    Concepts A sequence-else specification can branch to the same state... Sequence-advance specifications always to a previous state... branch to the next state. or a later state. Each state can have a unique storage specification. State Analyzer Sequencer with Four States Each state, except for the last, has two branch conditions.

  • Page 87

    Concepts Sequence-Else Specification The sequence-else branch, sometimes called the “else if” branch or secondary branch, may branch to any other state, including the current state, a previous state, or a later state. The sequence-else specification looks like the following: Else on “<TERM>” go to level <sequence level> If the Sequence-Else specification is satisfied before the sequence- advance specification is satisfied, the sequencer begins at <sequence level>.

  • Page 88

    Concepts you want to capture activity after the trigger is captured, define an additional sequence level and specify the desired storage qualification for post-trigger activity (for example, store “anystate”). Analyzer Resources The sequence-advance, sequence-else, storage, and trigger-on specifications are set by a combination of up to 10 pattern terms, 2 range terms, and 2 timers.

  • Page 89

    The following table shows how resources are divided in the HP 16550A. Remember that some resources may not be available, depending on the analyzer configuration. For example, if you are using the analyzer as a state analyzer, the Edge1 and Edge2 resources are not available.

  • Page 90

    Concepts So, the following combinations are valid combinations for the state analyzer, if timers are on: (a+b) • (In_Range2 + Timer2 > 400 ns) (c • Out_Range1) + (f xor g) The following combinations are not valid, because resources cross pair boundaries: (a + c) (d + Timer1 <...

  • Page 91

    5/6. Trying to define a range across pods 2/3, 4/5, or 1/6 will not work. The Timing Analyzer When you configure the HP 16550A as a timing analyzer, the trigger sequencer is similar. However, there are between 1 and 10 states available. The trigger term is always the last state. There are two additional resources, Edge1 and Edge2.

  • Page 92: The In Verse As Sem Bler

    The Inverse Assembler When the analyzer captures a trace, it captures binary information. The analyzer can then present this information in binary, octal, decimal, hexadecimal, or ASCII. Or, if given information about the meaning of the data captured, the analyzer can inverse assemble the trace.

  • Page 93

    Concepts The inverse assembler synchronizes at the first line in the trace list... not at the cursor position Inverse Assembly Synchronization If you roll the trace list to a new position and press Invasm again, the inverse assembler repeats the above process. However, it does not work backward in the trace list from the starting position.

  • Page 94

    Thus, you can have symbols in the address field without inverse-assembled data and status. The HP E2450A symbol download utility allows you to download symbols from OMF (Object Module Format) files.

  • Page 95: Con Figu Ra Tion Trans La Tion For Ana Lyzer Mod Ules

    HP 16500B Logic Analysis System to gain additional measurement features. Or, you might want to use a configuration file from one HP 16500B system on another HP 16500B with a different analyzer module. But, the analyzer configuration files cannot be transferred directly from one type of analyzer to the next.

  • Page 96

    The onscreen messages given by the translator will help you identify which analyzer pods must be swapped. If you are using an HP preprocessor, the Preprocessor User’s Guide may contain information showing the cable connections for different analyzer modules.

  • Page 97

    Concepts When you move a configuration file from one analyzer to another, the trace data from previous measurements is not moved. If you need to store trace data for future reference, see “To save a trace list in ASCII format” in chapter 3.

  • Page 99

    If You Have a Problem...

  • Page 100

    If You Have a Problem Occasionally, a measurement may not give the expected results. If you encounter difficulties while making measurements, use this chapter to guide you through some possible solutions. Each heading lists a problem you may encounter, along with some possible solutions. Error messages which may appear on the logic analyzer are listed below in quotes “...

  • Page 101: Ana Lyzer Prob Lems

    Analyzer Problems This section lists general problems that you might encounter while using the analyzer. Intermittent data errors This problem is usually caused by poor connections, incorrect signal levels, or marginal timing. Remove and reseat all cables and probes; ensure that there are no bent pins on the preprocessor interface or poor probe connections.

  • Page 102: No Setup/hold Field On For Mat Screen

    No Setup/Hold field on format screen No Setup/Hold field on format screen The HP 16540 and 16541 (A and D models), or HP 16542A logic analyzer cards are not calibrated. Refer to your logic analyzer reference manual for procedures to calibrate the cards.

  • Page 103: No Trace List Dis Play

    If You Have a Problem No trace list display If there is no trace list display, it may be that your analysis specification is not correct for the data you want to capture, or that the trace memory is only partially filled.

  • Page 104: Pre Proc Es Sor Prob Lems

    Preprocessor Problems This section lists problems that you might encounter when using a preprocessor. If the solutions suggested here do not correct the problem, you may have a defective preprocessor. Refer to the User’s Guide for your preprocessor for test procedures. Contact your local Hewlett-Packard Sales Office if you need further assistance.

  • Page 105: Slow Clock

    If You Have a Problem Slow clock Slow clock If you have the preprocessor interface hooked up and running and observe a slow clock or no activity from the interface board, the +5 V supply coming from the analyzer may not be getting to the interface board. To check the +5 V supply coming from the analyzer, disconnect one of the logic analyzer cables from the preprocessor and measure across pins 1 and 2 or pins 39 and 40.

  • Page 106

    If You Have a Problem Erratic trace measurements Try doing a full reset of the target system before beginning the measurement. Some preprocessor designs require a full reset to ensure correct configuration. Ensure that your target system meets the timing requirements of the processor with the preprocessor probe installed.

  • Page 107: In Verse As Sem Bler Prob Lems

    Inverse Assembler Problems This section lists problems that you might encounter while using the inverse assembler. When you obtain incorrect inverse assembly results, it may be unclear whether the problem is in the preprocessor or in your target system. If you follow the suggestions in this section to ensure that you are using the preprocessor and inverse assembler correctly, you can proceed with confidence in debugging your target system.

  • Page 108: In Verse As Sem Bler Will Not Load Or Run

    If You Have a Problem Inverse assembler will not load or run Check the activity indicators for status lines locked in a high or low state. Verify that the STAT, DATA, and ADDR format labels have not been modified from their default values. These labels must remain as they are configured by the configuration file.

  • Page 109: In Ter Mod Ule Meas Ure Ment Prob Lems

    Intermodule Measurement Problems Some problems occur only when you are trying to make a measurement involving multiple modules. An event wasn’t captured by one of the modules If you are trying to capture an event that occurs very shortly after the event that arms one of the measurement modules, it may be missed, due to internal analyzer delays.

  • Page 110: Mes Sages

    The default calibration file for the logic analyzer was loaded. The logic analyzer must be calibrated when using HP 16540A,D, HP 16541A,D or HP 16542A cards. Refer to the Logic Analyzer Reference for procedures to calibrate the master clocking system, and ensure that the “cal factors” file is saved.

  • Page 111: Meas Ure Ment Ini Tiali Za Tion Er Ror"

    “Measurement Initialization Error” This error occurs when you have installed the cables incorrectly for one or two HP 16550A logic analysis cards. The following diagrams show the correct cable connections for one-card and two-card installations. Ensure that your cable connections match the drawing, then repeat the measurement.

  • Page 112: No Con Figu Ra Tion File Loaded"

    “Slow or Missing Clock” This error message might occur if the logic analyzer cards are not firmly seated in the HP 16500A/B or HP 16501A frame. Ensure that the cards are firmly seated. This error might occur if the target system is not running properly.

  • Page 113: State Clock Vio Lates Over Drive Speci Fi Ca Tion"

    The error message “State Clock Violates Overdrive Specification” should occur only for HP 16510A,B, and HP 16511B Logic Analyzers with the Clock Period field set to <60 ns. If this error message is observed with the Clock Period set to >60 ns, you may have a faulty logic analyzer.

  • Page 114

    “Waiting for Trigger” If a “don't care” trigger condition is set, this message indicates: For an HP 16511B Logic Analyzer, only one of the two cards is receiving its state clock. Refer to “Slow or Missing Clock.” For an HP 16510A,B Logic Analyzer, the pattern duration is probably set to less than (<) instead of greater than (>).

  • Page 115

    Application Notes...

  • Page 116

    Application Notes Hewlett-Packard has prepared several application notes and product notes that show you how to get more out of your HP 16500B Logic Analysis System. Each note focuses on a particular application or problem, showing you the components of the problem, the approach required to solve it, the instrumentation, and the measurement results.

  • Page 117

    Application Note 1225-2 5091-5446E Cache Hit or Miss Analysis with Shows how to analyze cache hit the HP 16542A rate using the HP 16520A Pattern Generator with the HP 16542A deep memory state and timing module. Application Note 1225-3 5091-5447E...

  • Page 119

    The arm gathering by a signal is module. For usually used example, in to coordinate the HP 16532 measurement oscilloscope, start between one complete two or more cycle gathers measurement 8000 samples modules. of information...

  • Page 120

    For This field is example, in particularly important if HP 16532A, the input inadvertently coupling can select the be set to 1 Autoscale Mohm/DC, 1 field when Mohm/AC, you have your...

  • Page 121

    Glossary other. For deskewing To cancel or example, you nullify the can have an effects of external differences instrument between two arm a logic different analyzer, internal delay which paths for a subsequently signal. triggers an Deskewing is oscilloscope normally done when it finds by routing a the trigger...

  • Page 122

    Glossary ignore the either edge, state of this no edge, or signal when glitch (very determining short duration whether a pulse) on an match occurs input signal. on an input See also label. Don’t glitch. cares are glitch A glitch is represented defined as two by the X...

  • Page 123

    Glossary horizontal sweep speed In the vertical oscilloscope, scaling. the time value input impedance See coupling that field. determines intermodule menu The menu horizontal that allows scaling of the you to set up waveform to be displayed instrument to on the screen. make It is measured interactive...

  • Page 124

    Glossary s, it is choose any of represented the modules by an L in the in the pattern mainframe as selector. the working module. It manual markers mode The marker also allows mode for the you to choose timing system analyzer and options and oscilloscope...

  • Page 125

    This factor. For is normally example, in done in single- shot mode. HP 16532A, pattern mode For the the input oscilloscope, attenuation the trigger can be set mode that from 1:1 to...

  • Page 126

    ranges of analyzers, the values to be combination found on of patterns, labeled sets of occurrences, bits. For and time that example, a must be range of satisfied addresses to before the be found on trigger the address sequencer will bus or a range advance from of data values...

  • Page 127

    Glossary trigger. All of select the Run the transition field each matches that time you want lead to the a new trigger state acquisition must be satisfied corresponding before the screen analyzer will update. trigger. The skew Skew is the sequence is difference in defined by the...

  • Page 128

    Store analyzer. For qualification example, the allows you to HP 16550A specify the has twelve type of states in its information to trigger be stored in sequencer. memory. Use Each state has...

  • Page 129

    Glossary you begin to bit or set of troubleshoot a bits. See Also problem, you pattern terms, will probably range terms, want to qualify glitch/edge storage of all terms. activity. As timing sequence levels Similar to state understand sequence the problem levels.

  • Page 130

    Glossary touch-sensitive screen Any dark-blue trigger on the field on the first screen is a occurrence of “selectable” any kind field. When (trigger on “anystate”). you touch a dark-blue As you learn field, the field more about the problem toggles to another you are trying option, a pop-...

  • Page 131

    Glossary and you of patterns, specify trigger occurrences, on an address and time that is not on matching the a 32-bit trigger on boundary, term, it locks that address the contents will never of acquisition appear on the memory to address bus;...

  • Page 132

    Glossary placed in activity that memory. occurs before “Start” places the trigger. the trigger at “User- the start of Defined” lets memory and you specify fills the capture of a remainder of desired memory with amount of activity that posttrigger occurs after activity.

  • Page 133

    Glossary etc), and menu. It is a states toggle field captured after that allows the trigger are you to choose numbered whether to with positive trigger on the numbers (001, selected 002, etc). pattern when it is entered vertical position See offset or exited.

  • Page 134

    Glossary acquisition memory. Zooming and panning are useful in displaying single-shot waveforms. Glos sary16...

  • Page 135

    Glossary Glos sary17...

  • Page 136

    In dex Activation record, 1–7 else-if branch, 4–5 I/O activity, 2–20 Address bus, 4–10 Encapsulated PostScript files, 3–10 if branch, 4–4 Address ranges, 1–3 Entry address, 1–3 Independent clocks, 2–22 Analyzer Error Messages, 5–12 Independent lookup, 4–12 concepts, 4–2 External instrument Independent modules, 2–5 Analyzer problems, 5–3 starting or stopping, 2–9...

  • Page 137

    Sequence-Else specification, 1–2 Time stamps, 2–22 Sequential trigger, 1–2 Timer Control Field, 1–12, 1–18 Set up Timers, 4–6 Pair boundaries, 4–8 HP 16500B, 3–14 Trace lists Pairs, 4–7 Signals indented line numbers, 2–22 Pattern expression, 4–7 inserting and deleting, 2–24 interleaving, 2–20 to 2–22...

  • Page 138

    Index Verifying chip select line is strobed, 1–17 correct execution, 1–3 correct storage, 1–13 efficiency, 1–3 Viewing trace lists and waveforms together, 2–25 Watchdog timer behavior, 2–20 Waveforms deleting, 2–27 inserting, 2–27 viewing with trace lists, 2–25 In dex3...

  • Page 139

    In dex4...

  • Page 140

    Hewlett-Packard P.O. Box 2197 1900 Garden of the Gods Road Colorado Springs, CO 80901...

  • Page 141

    ©...

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16501a

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