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2D DIGITAL SCHEMATIC DIAGRAMS [HR-XVS30EK, HR-XVS30EX]
5
4
3
LC1201
100^
C1246
47
/6.3
2
TO MAIN(S-SUB)
C1203
C1204
CN501
OPEN
OPEN
CN1201
R1203
I2C_DATA
R1204
I2C_CLK
R1205
KILLER_DET
C_FROM_DIGI
GND
Y_FROM_DIGI
EE[L]
V/Y_TO_DIGI
C1208
SW5V[2]
C_TO_DIGI
C1209
R1206
GND
560
Fsc
1
L1201
1^
A
R1210
39k
0.5%
L1204
220^
Q1201
2SC1317/RS/
C1220
47
/6.3
R1201
R1202
120
100
R1212
1k
C1243
0.01
C1201
47
/6.3
D1201
RD4.3ES/B3/
Q1202
R1215
1k
C1244
4.7
/25
220
220
1k
Q1203
100p
OPEN
C1210
33p
B
C
C1212
0.001
C1211
47
/6.3
R1207
5.6k
L1202
R1208
180'
12k
IC1201
JCP8036
JCP8057
C1215
47
/6.3
L1203
330^
IIC_DATA
IIC_CLK
RESET
CMUTE
VSS
C1217
0.1
VDD
C1218
0.1
VREF
VR1201
R1211
COUT
SHORT
15k
0.5%
IOB
C1219
1
R1223
R1221
OPEN
COMP
OPEN
YOUT
R1214
R1217
R1218
82
75
300
0.5%
0.5%
L1205
SHORT
C1223
R1213
C1222
OPEN
C1228
OPEN
OPEN
4.7
/25
2SC4081/S/
L1206
R1225
SHORT
R1220
OPEN
0'
C1248
C1226
OPEN
R1216
C1225
OPEN
OPEN
OPEN
R1226
R1228
OPEN
OPEN
D
E
2-21
2-22
C1216
0.1
NC( TEST)
NC( TEST)
NC( TEST)
C1237
0.1
FSC_IN
VDD
C1236
0.1
VSS
NC( TEST)
NC( TEST)
NC( TEST)
NC( TEST)
AVDD
C1234
0.1
R1224
560
C1229
0.01
Q1205
L1208
SHORT
R1227
Q1204
OPEN
Q1206
OPEN
C1238
OPEN
C1245
C1239
OPEN
OPEN
R1222
OPEN
F
L1207
220^
C1235
47
/6.3
p20370001a_rev0
G
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