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XV-S56BK/XV-S57SL
ZIVA-4.1-PA2(IC501):Back end - Digital decoder
1.Terminal layout
~
208
157
1
52
~
53
104
2.Pin function (1/5)
Pin No.
Symbol
1
RD
2
R/W
3
VDD
4
WAIT
5
RESET
6
VSS
7
VDD
8
INT
9
NC
10
NC
11
NC
12
NC
13
VDD
14
VSS
15
NC
16
NC
17
NC
18
NC
19
VSS
20
VDD
21
VDATA0
22
VDATA1
23
VDATA2
24
VDATA3
25
VDATA4
26
VDATA5
27
VDATA6
28
VDATA7
29
VSYNC
30
HSYNC
31
VSS
32
VDD
33
NC
34
NC
35
NC
36
VDD
1-34
156
105
I/O
Read strobe input
I
Read/write strobe input
I
Power supply terminal 3.3V
-
O
Transfer not complete / data acknowledge.
Active LOW to indicate host initiated transfer is complete.
Active LOW : reset signal input
I
-
Connect to ground
Power supply terminal 3.3V
-
Host interrupt signal output
O
Non connect
-
Non connect
-
Non connect
-
Non connect
-
Power supply terminal 2.5V
-
-
Connect to ground
Non connect
-
Non connect
-
-
Non connect
Non connect
-
Connect to ground
-
Power supply 3.3V
-
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
O
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
O
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
O
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
O
O
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
O
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
O
O
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
Vertical sync. Bi-directional, the decoder output the top border of a new
I/O
field on the first HSYNC after the falling edge of VSYNC.
Horizontal sync. The decoder begins outputting pixel data for a new
I/O
horizontal line after the falling (active) edge of HSYNC.
Connect to ground
-
Power supply terminal 3.3V
-
Non connect
-
-
Non connect
Non connect
-
Power supply terminal 2.5V
-
Description
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