Integra DTR-7.6 Service Manual page 91

IC BLOCK DIAGRAMS AND DESCRIPTIONS
BR24L02FV-W/08FV-W(256X8 bit EEPROM)
1
A0
Address
2
A1
Decorder
3
A2
High-voltage
4
GND
generation circuit
Terminal
Vcc
GND
A0,A1,A2
SCL
SDA
WP
2k Bit EEPROM Array
8bit
Slave word
8bit
address register
START STOP
Control circuit
Power voltage
detection
I/O
Function
-
Apply a power source.
-
Ground termional
I Slave address setting terminal
Serial clock input
I
Slave and word address.
I/O
Serial data input and output
I
Write protect terminal
8
8bit
Data
7
register
6
ACK
5
DTR-7.6
Vcc
WP
SCL
SDA