Integra DTR-7.6 Service Manual page 84

ADV7172 (Digital PAL/NTSC Video Encoder with Six DACs (10-Bits))
BLOCK DIAGRAM
48 43
14
HSYNC
FIELD/
VIDEO TIMING
15
VSYNC GENERATOR
16
BLANK
RESET 44
TTX 41
TELETEXT
INSERTION BLOCK
TTXREQ 40
8
VCrCb
4:2:2 TO
P0-P7
2 TO
8
4:4:4
| YUV
(COLOR
INTER-
9 MATRIX
POLATOR
DATA)
8
PIN LAYOUT
10 45 14 20 21
2
I C MPU PORT
BRIGHTNESS AND
CONTRAST CONTROL
10
ADD SYNC
Y 8
INTERPOLATOR
U
SATURATION CONTROL
10
8
ADD BURST
10
V 8
INTERPOLATOR
REAL-TIME
CONTROL CIRCUIT
39
SCRESET/RTC
48 47 46 45 44 43 42 41 40 39 38 37
V
1
AA
P0
2
P1
3
P2
4
P3
5
P4
6
TOP VIEW
P5
7
P6
8
P7
9
CSO_HSO
10
V
11
AA
GND
12
13 14 15 16 17 18 19 20 21 22 23 24
17
YUV TO
RGB
MATRIX
YUV
LEVEL
CONTROL
BLOCK
LUMA
PROGRAMMABLE
FILTER
SHARPNESS
FILTER
MODULATOR
PROGRAMMABLE
CHROMA
HUE
FILTER
CONTROL
10 10
SIN/COS
DDS SLOCK
12,13,18,26,31,47
GND
COMP1
36
DAC A
35
V
34
AA
DAC B
33
V
32
AA
GND
31
V
30
AA
DAC C
29
DACD
28
V
27
AA
GND
26
DAC E
25
DTR-7.6
10 10
10BIT
35 DAC A
DAC
10
10
10BIT
33 DAC B
DAC
10
10
10BIT
29
DAC C
DAC
37 VREF
DAC
CONTROL 22
RESET2
BLOCK
23 COMP2
10
10BIT
25 DAC E
DAC
10
10
10BIT
10 24
DAC F
DAC
10 10
10BIT
28
DAC D
DAC
DAC
38 RESET1
CONTROL
BLOCK
36
COMP1