Integra DTR-7.6 Service Manual page 86

IC BLOCK DIAGRAMS AND DESCRIPTIONS
ADV7183 (Advanced Video Decoder with 10-Bit ADC and Component Support)
BLOCK DIAGRAM
ADV7183
ISO
REFOUT
AIN1
ANALOG I/P
AIN2
MULTIPLEXING
AUTOMATIC
AIN3
GAIN
CONTROL
(AGC)
AIN4
CLAMP AND
AIN5
DC RESTRE
AIN6
PWRDN
TERMINAL DESCRIPTION
Pin Mnemonic
1 VS/VACTIVE
2 HS/HACTIVE
3, 14 DVSSIO
4, 15 DVDDIO
5-8, 19-24, P15-P0
32, 33, 73-76
9, 31, 71 DVSS1-3
10, 30, 72 DVDD1-3
11 AFF
12 HFF/QCLK/GL
13 AEF
16 CLKIN
17, 18, 34, 35 GPO[3:0]
SHAPING
PEAKING
AND
HPF/LPF
NOTCH LPF
LUMA
10-BIT
ANTIALIAS
ADC
LPF
CARRIER
27MHz
RECOVERY
CHROMA
10-BIT
SWITCH ANTIALIAS
ADC
VIDEO TIMING AND
CONTROL BLOCK
HSYNC FIELD VSYNC HREF VREF
Input/Output Function
O VS or Vertical Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is an
output signal that indicates a vertical sync with respect to the YUV pixel
data. The active period of this signal is six lines of video long. The polarity
of the VS signal is controlled by the PVS bit. VACTIVE (OM_SEL[1:0] =
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video field. The polarity of VACTIVE is controlled by PVS bit.
HS or Horizontal Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is a
O
programmable horizontal sync output signal. The rising and falling edges
can be controlled by HSB[9:0] and HSE[9:0] in steps of 2 LLC1. The polarity
of the HS signal is controlled by the PHS bit. HACTIVE (OM_SEL[1:0]=
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video line. The active portion of a video line is programmable on
the ADV7183. The polarity of HACTIVE is controlled by PHS bit.
G Digital I/O Ground
P Digital I/O Supply Voltage (3.3 V)
O Video Pixel Output Port. 8-bit multiplexed YCrCb pixel port (P15-P8),
16-bit YCrCb pixel port (P15-P8 = Y and P7-P0 = Cb,Cr).
G Ground for Digital Supply
P Digital Supply Voltage (3.3 V)
O Almost Full Flag. A FIFO control signal indicating when the FIFO has
reached the almost full margin set by the user (use FFM[4:0]). The polarity
of this signal is controlled by the PFF bit.
I/O Half Full Flag. A multifunction pin, (OM_SEL[1:0] = 1, 0) is a FIFO
control signal that indicates when the FIFO is half full. The QCLK
(OM_SEL[1:0] = 0, 1) pin function is a qualified pixel output clock when
using FIFO SCAPI mode. The GL (OM_SEL[1:0] = 0, 0) function
(Genlock output) is a signal that contains a serial stream of data that contains
information for locking the subcarrier frequency. The polarity of HFF signal
is controlled by PFF bit.
O Almost Empty Flag. A FIFO control signal, it indicates when the FIFO
has reached the almost empty margin set by the user (use FFM[4:0]). The
polarity of this signal is controlled by PFF bit.
I Asynchronous FIFO Clock. This asynchronous clock is used to output
data onto the P19-P0 bus and other control signals.
O General-Purpose Outputs controlled via I C
RESAMPLING LUMA
AND
DELAY
HORIZONTAL
BLOCK
SCALING
SYNC 2H LINE
MEMORY
DETECTION
RESAMPLING
SUB-
CHROMA
AND
COMB
HORIZONTAL
FILTER
DTO SCALING
SHAPING
LPF
LPF
27MHz XTAL
I 2 C-COMPATIBLE
OSCILLATOR
INTERFACE PORT
BLOCK
CLOCK CLOCK RESET SDATA
2
P15-P0
PIXEL
O/P POR T
FIFO CONTROL
BLOCK
AND
PIXEL
OUTPUT
FORMATTER
LLC
SYNTHESIS
WITH LINE-
LOCKED
OUTPUT
CLOCK
SCLOCK ALSB
DTR-7.6
AFF
HFF/QCLK
AEF
DV
RD
OE
GL/CLKIN
LLC1
LLC2
LLCREF
ELPF