Epson E0C6006 Technical Manual page 47

• Timer Interrupt
As described in section 4.8 "Clock Timer", the timer signal of 2 Hz, 8 Hz or 32 Hz can request a timer
interrupt (when f
OSC1
state, the CPU can be restarted under timer control.
• REM Interrupt
As described in section 4.9 "Remote Controller", a REM interrupt can be invoked during operation of
the REM circuit or synchronously with a REM carrier. Note that the operation of the REM circuit is
assured only with a CPU clock being supplied from OSC3.
• Input Interrupt
An input interrupt can be invoked by the IK1 group (K10–K13) or the IK0 group (K00–K03). As each
pin contains an f
OSC1
least 16/f (0.5 msec) to assure an input interrupt.
OSC1
For the K10–K13 group, the interrupt factor flag can be set with the noise reject circuit bypassed by
using the mask option. In this case, the input must be held at low level for at least 5 machine clocks
(equivalent to 0.16 msec in the 32 kHz mode or 11 µsec in the 455 kHz mode) to get an assured input
interrupt.
Since the noise reject circuit continues operating with the CPU in the halt state, the CPU can be
restarted by an input interrupt. Note that, if this is impossible, initial resetting under watchdog timer
control is required.
K13
K12
K11
K10
K03
K02
K01
K00
E0C6006 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
= 32.768 kHz). As the timer continues to operate even with the CPU in the halt
f
OSC1
(32.768 kHz)
Timer
TMRUN
Fig. 4.10.1.1 Timer interrupt request circuit
/8 (4 kHz) clock noise reject circuit, the input must be held at low level for at
f /8 (4 kHz)
OSC1
Fig. 4.10.1.2 Input interrupt circuit
Interrupt factor flag
2 Hz
T I 2
(Falling edge)
8 Hz
T I 8
(Falling edge)
32 Hz
T I 3 2
(Falling edge)
Noise reject
circuit
Mask option
Noise reject
circuit
EPSON
Interrupt factor flag
IK1
(Falling edge)
IK0
(Falling edge)
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