RCA 301 Programmer's Reference Manual page 68

Q Logical "OR" (OR)
s/sf^r
General Description
This instruction is one of three instructions which provides the 301 system with bit manipulation abilities.
It operates on equal length operands according to the rules outlined under "Outline of Operation below.
Format
Operation — Q
N —Number (0-44) of characters in each operand. (See Appendix F-I.)
A Address — HSM location of least significant digit of first operand and result.
B Address — HSM location of least significant digit of second operand.
Direction of Operation
Right to left.
Outline of Operation
This instruction operates in the following cycle:
The contents of the N Register are examined. If zero, the instruction terminates. If other than zero, the
contents of the HSM location specified by the A Register are combined bit by bit with the contents of the HSM
location specified by the B Register. This bit manipulation is combined according to the following rules:
Bit in
First Operand
0
0
1
1
The result of the combination is placed in the HSM location specified by the A Register. The contents of the
A, B, and N Registers are decremented by one and the instruction is repeated.
All six information bits of each operand enter the operation. The proper parity for each result character is
generated as part of this instruction.
Example of Rules
(a) 1 00 1001
1 01 0001
0 01 1001
Final Register Contents
(A) = Address of location one to the left of the most significant digit of the result.
f
(B) — Ad dress of location one to the left of the most significant digit of second operand.
t
Timing
Total time in microseconds
= 21n + 35, where n is the number of characters in either operand (operands must be of equal lengths).
VI-8
bits.
Bit in
Second Operand
0
1
0
1
(b) 0 11 0001
0 10 0011
1 11 0011
Repeatable
Bit in Result Bit in Result
0
1
1
1