Maxim Integrated MAX32600 Manuals

Maxim Integrated MAX32600 Manuals

Manuals and User Guides for Maxim Integrated MAX32600. We have 1 Maxim Integrated MAX32600 manual available for free PDF download: User Manual

Maxim Integrated MAX32600 User Manual

Maxim Integrated MAX32600 User Manual (687 pages)

Wellness Measurement Microcontroller

Brand: Maxim Integrated | Category: Microcontrollers | Size: 13 MB

Table of Contents

Table of Contents
2
1 Main Page

20
- Legal Disclaimer
  20
- Revision Information
  20
2 Introduction

22
- Overview
  22
- Core and Architecture
  24
  - Core Parameters
    24
  - Generic Memory Map
    26
  - AHB Buses
    27
  - APB Buses
    27
  - Nested Vectored Interrupt Controller (NVIC)
    27
  - ARM Debug
    28
- Power Supplies and Modes
  28
- Clock Inputs
  30
- External High Frequency Crystal
  30
- Memory
  31
  - Internal Flash Program Memory
    31
  - KB Instruction Cache
    31
  - Internal Data SRAM
    32
  - Peripheral Management Unit (PMU)
    32
  - Flash Information Block
    33
  - Flash Memory Controller
    33
- Analog Peripherals
  34
- Digital Peripherals
  35
  - GPIO Pins W/Interrupt and Wakeup Capability
    35
  - 32-Bit Timer/Counters
    36
  - Watchdog Timers
    36
  - 32-Bit Real Time Clock with Time of Day Alarm
    37
  - SPI (Three Instances)
    37
  - I²C
    37
  - USB 2.0 Device Slave with Integrated Transceiver
    38
  - LCD Controller
    38
  - Security Features
    39
  - Trust Protection Unit (TPU)
    39
  - AES Cryptographic Engine
    39
  - Battery-Backed AES Secure Key Storage
    39
  - Modular Arithmetic Accelerator (MAA)
    40
  - CRC Hardware Block with CRC16 and CRC32
    40
  - Code Scrambling
    40
3 Memory, Register Mapping, and Access

41
4 System Conﬁguration and Management

47
- Power Ecosystem and Operating Modes
  47
  - Power Ecosystem
    47
  - Low Power Modes (LP0: STOP and LP1: STANDBY)
    49
    
    Low Power Mode 0 (LP0: STOP)
    49
    
    Low Power Mode 1 (LP1: STANDBY)
    49
    
    Entering LP0: STOP or LP1: STANDBY
    50
    
    Wakeup Events from LP0: STOP and LP1: STANDBY
    51
  - Low Power Modes (LP2: PMU and LP3: RUN)
    52
    
    Low Power Mode 2 (LP2: Peripheral Management Unit)
    53
    
    Low Power Mode 3 (LP3: RUN)
    53
  - Power State Matrix Control Options
    53
  - Power Domains
    55
  - Power Manager
    56
  - Power Sequencer
    56
    
    Power Mode Transitioning to Low Power Modes
    56
    
    Supply Voltage Monitoring During LP0: STOP and LP1: STANDBY
    56
    
    First Boot Power up
    57
    
    SVM Periodic Monitoring
    57
    
    Brownout Detector
    58
    
    Trickle Charger
    58
    
    Trickle Charger Conﬁguration
    58
    
    Ldo
    59
    
    Low-Dropout Regulators (LDO)
    59
    
    Usb Ldo
    59
  - Reset Pins
    60
  - Power Pins
    60
  - Registers (PWRMAN)
    61
    
    Module PWRMAN Registers
    61
  - Registers (PWRSEQ)
    88
    
    Module PWRSEQ Registers
    88
- Interrupt Vector Table
  118
- Resets and Reset Sources
  120
  - System Reset
    120
  - Power-On Reset
    121
  - Rtc por
    121
- Registers (IOMAN)
  121
  - Module IOMAN Registers
    121
    
    Ioman_Ali_Req0
    121
    
    Ioman_Ali_Req1
    121
    
    Ioman_Wud_Ack0
    121
    
    Ioman_Wud_Ack1
    121
    
    Ioman_Wud_Req0
    121
    
    Ioman_Wud_Req1
    121
    
    Ioman_Spi0_Req
    122
- Ioman_Spi1_Req
  137
- Ioman_Spi1_Ack
  140
- Ioman_Spi2_Req
  142
- Ioman_Spi2_Ack
  145
- Ioman_Uart0_Req
  148
- Ioman_Uart0_Ack
  149
- Ioman_Uart1_Req
  150
- Ioman_Uart1_Ack
  151
- Ioman_I2Cm0_Req
  152
- Ioman_I2Cm0_Ack
  153
- Ioman_I2Cs0_Req
  154
- Ioman_Lcd_Com_Req
  155
- Ioman_Lcd_Seg_Req1
  163
- Ioman_Lcd_Seg_Ack0
  165
- Ioman_Lcd_Seg_Ack1
  173
- Ioman_Crnt_Req
  175
- Ioman_Crnt_Ack
  176
- Ioman_Crnt_Mode
  178
- Ioman_Ali_Connect0
  179
- Ioman_I2Cm1_Ack
  180
  - Pin Layout
    183
    
    5.2 Pin Function Mapping
    184
    
    5.2 Pin Function Mapping
    185
    
    5.2 Pin Function Mapping
    186
    
    5.2 Pin Function Mapping
    187
    
    5.2 Pin Function Mapping
    188
    
    5.2 Pin Function Mapping
    189
    
    5.2 Pin Function Mapping
    190
    
    5.3 General-Purpose I/O
    191
    
    5.3 General-Purpose I/O
    192
    
    5.4 GPIO Pins and Peripheral Mode Functions
    193
    
    5.4 GPIO Pins and Peripheral Mode Functions
    194
    
    5.4 GPIO Pins and Peripheral Mode Functions
    195
    
    5.4 GPIO Pins and Peripheral Mode Functions
    196
    
    5.4 GPIO Pins and Peripheral Mode Functions
    197
    
    5.5 Registers (GPIO
    198
    
    5.5 Registers (GPIO
    199
    
    5.5 Registers (GPIO
    200
    
    Gpio_Free_Pn
    201
    
    Gpio_Out_Mode_Pn
    202
    
    Gpio_Out_Val_Pn
    203
    
    5.5 Registers (GPIO
    204
    
    5.5 Registers (GPIO
    205
    
    5.5 Registers (GPIO
    206
    
    Gpio_In_Mode_Pn
    207
    
    Gpio_In_Val_Pn
    208
    
    Gpio_Int_Mode_Pn
    209
    
    Gpio_Inten_Pn
    210
  - PMU Operation
    213
    
    Rev.1.3 April
    214
    
    6.3 PMU Programming Details
    215
    
    6.3 PMU Programming Details
    216
    
    6.3 PMU Programming Details
    217
    
    6.3 PMU Programming Details
    218
    
    6.3 PMU Programming Details
    219
    
    6.3 PMU Programming Details
    220
    
    6.3 PMU Programming Details
    221
    
    6.3 PMU Programming Details
    222
    
    6.3 PMU Programming Details
    223
    
    6.3 PMU Programming Details
    224
    
    6.3 PMU Programming Details
    225
  - Registers (PMU)
    226
    
    Pmun_Cfg
    229
    
    Pmun_Loop
    232
    
    Pmun_Dsc1
    233
    
    Communication Peripherals 7.1 I²C
    234
    
    Protocol
    241
    
    Rev.1.3 April
    242
    
    FIFO-Based I²C Master
    246
5 Pin Configurations, Packages, and Special Function Multiplexing

183
6 Peripheral Management Unit (PMU)

213
- Module I2CM Registers
  248
- Module I2CS Registers
  258
- Clock Gating
  281
- Static Conﬁguration
  282
- Module SPI Registers
  287
  - Uart
    301
    
    Rev.1.3 April
    302
    
    Clear to Send
    306
    
    Ready to Send
    307
    
    USB Reset Deﬁnitions
    319
    
    Endpoint Control Register
    321
    
    Endpoint Buffer Descriptor
    322
    
    Module USB Registers
    323
  - AFE Overview
    358
  - Rev.1.3 April
    359
8 Analog Front End

358
- Comparators
  369
- Module AFE Registers
  371
- Input Multiplexer
  428
- Scan Modes
  431
- Interrupts
  432
- Sample Rate Calculation
  435
- Start the Measurement
  440
  - Rev.1.3 April
    470
  - Reduced Power Level Modes for 12-Bit DAC Instances
    474
  - Correcting for Distortion at High Output Frequency
    479
  - Module DAC Registers
    480
  - LED Driver Details
    489
    
    LED Conﬁguration
    490
    
    Basic LED Conﬁguration
    491
    
    Multiple LED Conﬁguration
    492
    
    H-Bridge LED Conﬁguration
    493
    
    Independent Loop H-Bridge LED Conﬁguration
    494
    
    Integrated Feedback Loops LED Conﬁguration
    495
    
    Internal Feedback with Common Sense Resistor LED Conﬁguration
    496
    
    Double H-Bridge LED Conﬁguration
    497
    
    Multiple High Voltage LED Control Conﬁguration
    498
    
    Register Conﬁgurations
    500
    
    Control Loop Setup
    503
    
    Fault Detection Setup
    504
    
    Design Current
    505
    
    Enabling and Disabling Pulse Train Outputs 9.4.1 Master Enable/Disable
    508
    
    Square Wave Mode
    510
    
    Ptg_Ctrl
    512
    
    Ptn_Rate_Length
    514
    
    System Clock
    516
    
    Khz Crystal Oscillator
    518
    
    Rev.1.3 April
    519
    
    External Clock
    520
    
    External 32Khz Clock (Crystal or Resonator)
    522
    
    Phase Lock Loop
    523
    
    Relaxation Oscillator
    525
    
    Crypto Clock Relaxation Oscillator
    526
    
    ADC Clock Source Conﬁguration
    527
    
    Registers (CLKMAN)
    528
    
    Watchdog Timers
    572
    
    Watchdog Timers Overview
    573
    
    Watchdog Timer Conﬁguration
    574
    
    Enabling and Disabling the Watchdog Timer Counter
    575
  - Real Time Clock (RTC)
    581
    
    RTC Resets
    582
    
    RTC Conﬁguration
    583
    
    Registers (RTCTMR)
    586
    
    Timers/Counters Overview
    604
    
    Bit Mode Timer Operation
    606
    
    Continuous Mode
    607
    
    Counter Mode
    608
    
    PWM Mode
    609
    
    Capture Mode
    611
    
    Gated Mode
    612
    
    Capture/Compare Mode
    613
    
    Bit Mode Timer Operation
    614
    
    One-Shot Mode
    615
    
    Registers (TMR)
    616
    
    Registers (AES)
    626
    
    Rev.1.3 April
    627
11 Trust Protection Unit (TPU)

626
- Modular Arithmetic Accelerator (MAA)
  635
  - Registers (MAA)
    636
- Registers (TPU)
  644
  - Tpu_Tsr_Status
    645
  - Tpu_Tsr_Ctrl1
    647
  - Tpu_Tsr_Sks0
    648
  - CRC16 and CRC32 Hardware Accelerator 12.1 Overview
    649
- CRC-16-CCITT Example Calculation
  650
  - Crc_Reseed
    651
  - Crc_Seed32
    652
  - Rev.1.3 April
    653
13 LCD Controller

654
- LCD Operation
  654
  - LCD Conﬁguration
    655
  - LCD Internal Register Adjust
    656
    
    LCD Port Conﬁguration
    658
    
    LCD Memory Conﬁguration
    659
- Registers (LCD)
  660
  - Lcd_Lcra
    662
  - Lcd_Lpcf
    664
  - Lcd_Lcdata
    665
14 Flash Controller and Instruction Cache

668
- Registers (FLC)
  668
  - Flc_Faddr
    669
  - Flc_Ctrl
    670
  - Rev.1.3 April
    671
  - Flc_Intr
    673
  - Flc_Fdata
    674
  - Flc_Status
    675
  - Flc_Security
    676
  - Flc_Bypass
    677
  - Flc_User_Option
    678
  - Flc_Ctrl2
    679
  - Flc_Intfl1
    680
  - Flc_Inten1
    681
  - Flc_Disable_Xr1
    682
  - Flc_Disable_Xr3
    683
  - Flc_Disable_We1
    684
- Registers (ICC)
  685
  - Icc_Mem_Cfg
    686
  - Icc_Invdt_All
    687

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