ON Semiconductor NB3x6x1xxG8DFN Manual

NB3x6x1xxG8DFNEVK
NB3x6x1xxG8DFN
OmniClock Evaluation
Kit Manual
Devices Supported
•
NB3H60113G (DFN8, 3.3 V)
•
NB3V60113G (DFN8, 1.8 V)
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Introductio
NB3x6x1xxG8DFNEVK is an evaluation kit offering a
convenient solution for evaluating DFN8 devices. Included
are one main board, a daughter board, and a USB cable. The
main board and daughter board are 4 layer boards with
dedicated power and GND planes.
The daughter board plugs directly on to the main board
using four 4−pin header connectors. These connectors route
the signal, power and ground to the device on the daughter
board. The two boards correctly plug into one another in
only one orientation ensuring proper pin alignment. The
daughter board has a DFN8 socket to test NB3x6x1xxG
devices. A view of the main board with the DFN8 daughter
board is shown in Figures 1 and 2.
The Clock Cruiser Software is the GUI software
developed to be used with this evaluation kit, and can be
downloaded for free from www.onsemi.com. It allows the
user to set programmable parameters and generate solutions
that fit application needs. These solutions can then be
programmed in to device's OTP memory or be temporarily
written into device registers for evaluation. For more
information on using the GUI, refer to Clock Cruiser User
Guide.
Figure 1. 455 View of Main Board with DFN8
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 1
Daughter Board
EVAL BOARD USER'S MANUAL
Description
The NB3x6x1xxG, which is a member of the OmniClock
family, is a versatile user programmable clock generator
designed by ON Semiconductor with customer experience
in mind. These devices are tailored to fit into an extensive
array of applications including wearable technology, smart
phones, digital cameras, E−books, portable electronics, and
Internet of Things. The NB3H designated parts are powered
by 3.3 V and 2.5 V supplies while NB3V parts support 1.8
V operation.
These devices are One Time Programmable (OTP), low
power PLL based clock generators that accept fundamental
mode parallel resonant crystals of up to 50 MHz or a single
ended LVCMOS/LVTTL reference clock input of up to
200 MHz. The outputs can be configured as either three
single ended LVCMOS/LVTTL outputs or a combination of
one single ended
LVPECL/LVDS/HCSL/CML output. The generated clock
output's frequency can range between 8 kHz to 200 MHz.
Other programmable parameters include internal crystal
load capacitor, drive strength for LVCMOS outputs, output
frequency modulation controls (type, depth, modulation
rate), output phase inversion, and PLL bypass mode. The
devices are fully functional between −40°C to +85°C.
Figure 2. Top View of Main Board with DFN8
1
www.onsemi.com
output and one differential
Publication Order Number:
EVBUM2358/D