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5. LCD display section
(1) Block diagram
MC
Counter
PNC
AUDCL
AUDCP
Auditor
AUDO
AUDRD
+12V
+5V
PCU
GND2
+24V
PWB
-20V
GND1
RXD-OP
DSR-OP
Driver
TXD-OP
DTR-OP
IC329
RES-OP
LATCH
CLK
Driver
BEO
DATA
IC325
KI1
KI2
Q403
KI3
KI4
IC326
KI5
OP
PWB
IC324
OPTS
O P TR
Q404
PTH A/B
CCFT
Invertor
VRA
VRB
+5VLCD
-19VLCD
LCD unit
S
CP1
CP2
Buffer
D0
D1
IC327
D2
D3
LCD,VR
PWB
(2) CPU (IC321) µPD78217GC-AB8
1
Outline
The CPU sends and receives data to and from the main circuit and
the operation PWB through the serial data communication line, and
controls the display system.
LCD control
Copier main
PWB
circuit
CPU
Display data
output
Key input
LCD controller
data input
DATA
ROM
Driver
IC315
IC304,329
PRO-
GRAM
ROM
IC314
RD
A0 ~ A19
D0 ~ D7
CPU
IC321
Decoder
IC318
IC319
5VREM
Q402
+12V
-19VREM
IC328
Q302
-20V
IC323
Operation PWB
LED display data input
Key input data output
LED display section
D0 ~ D7
A0 ~ A15
CS
CS
LCD
controller
IC322
MD ~ MD15
Timing
MCLK
DCLK
section
A17
CS
IC406
ASTB
IC408
LC-RES
IC410
IC405
IC409
IC320
2
Pin arrangement
P64/RD
1
P63/A19
2
P62/A18
3
P61/A17
4
P60/A16
5
RESET
6
X2
7
X1
8
VSS
9
P57/A15
10
P56/A14
11
P55/A13
12
P54/A12
13
P53/A11
14
P52/A10
15
16
P51/A9
9 – 17
A-RAM
V-RAM
Buffer
IC301
A0 ~ A12
IC310
IC302
IC311
IC303
IC235
MCLK
WR
CS
Buffer
IC312
IC313
MCLK
G-ROM
Latch
Latch
CG
IC401
IC404
-ROM
IC402
IC407
IC403
IC305
IC309
48
47
46
45
44
43
42
41
µPD78217GC-AB8
40
39
38
37
36
35
34
33
Buffer
IC306
IC307
IC308
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
AVREF
AVSS
VDD
EA
P33/SO/SB0
P32/SCK
P31/TXD
P30/RXD
P27/SI
P26/INTP5
P25/INTP4
/ASCK
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