Table of Contents
Advertisement
Gate array B
Pin arrangement table
No.
Pin name
I/O
Function
1
GND
2
VCC
3
AIN0
IN
*
*
*
(n) Line image data input pin.
10
AIN7
IN
Signals according to each mode
11
RAMADR0
OUT
such as the result of area separation
*
*
*
are outputted to the external LUT
14
RAMADR3
OUT
from this pin.
15
GND
Signals according to each mode
16
RAMADR4
OUT
such as the result of area separation
*
*
*
are outputted to the external LUT
19
RAMADR7
OUT
from this pin.
20
VCC (fixed)
211
GND (fixed)
22
GND
23
BIN0
IN
*
*
*
(n+1)the line image data input pin
30
BIN7
IN
31
RESERVED
Not used.
Signals according to each mode
32
RAMADR8
OUT
such as the result of area separation
*
*
*
are outputted to the external LUT
34
RAMADR10
OUT
from this pin.
35
GND
Signals according to each mode
36
RAMADR11
OUT
such as the result of area separation
*
*
*
are outputted to the external LUT
39
RAMADR14
OUT
from this pin.
40
GND
41
RAMDATA0
IN
Pin for data input from the external
*
*
*
LUT.
48
RAMDATA7
IN
49
FILOUT0
OUT
Pin for output of the result of filter
*
*
*
process.
52
FILOUT7
OUT
53
GND
54
FILOUT4
OUT
Pin for output of the result of filter
*
*
*
process.
57
FILOUT7
OUT
Clock signal input pin. Clock of
58
CLK1
IN
16MHz is inputted.
59
GND
60
VCC
61
GND (fixed)
62
VCC (fixed)
63
CIN0
IN
*
*
*
(n+2)the line image data input pin
70
CIN7
IN
71
XIFDAT0
I/O
*
*
*
Data bus to set the built-in register.
78
XIFDAT7
I/O
79
GND
80
DIN0
IN
*
*
*
(n+3)the line image data input pin
87
DIN7
IN
88
RESET
IN
Reset signal of the LSI
89
XIFADR0
IN
Address bus to select the built-in
*
*
*
register.
94
XIFADR5
IN
No.
Pin name
I/O
95
AREALDLY
OUT
96
CLK2
97
XIFRD
98
XIFWR
99
XIFEN
100
VCC (fixed)
101
GND (fixed)
102
BUNRIOUT0
OUT
*
*
*
105
BUNRIOUT3
OUT
106
GND
107
BUNRIOUT4
OUT
*
*
*
112
BUNRIOUT9
OUT
113
GND
114
CLK3
115
ZOOMIN0
*
*
*
125
ZOOMIN10
126
GND
127
ZOOMOUT0
*
*
*
130
ZOOMOUT3
131
GND
132
ZOOMOUT4
*
*
*
135
ZOOMOUT7
136
GND
137
VCC
138
ZOOMOUT8
*
*
*
140
ZOOMOUT10
141
FIFOWEN
OUT
142
VCC (fixed)
143
GND (fixed)
144
GND
145
FIFOREN
OUT
146
RAMDLY0
OUT
*
*
*
148
RAMDLY2
OUT
149
AREAHDLY
OUT
150
HSYNC
151
AREA
OUT
152
EIN0
*
*
*
159
EIN7
160
PAGE
1 – 10
Function
Signal showing the effective image
area which is behind from AREA
signal by 4 clocks. LOW active.
Clock signal input pin. Clock of
IN
16MHz is inputted.
Data read signal to the built-in
IN
register.
LOW active.
Data write signal to the built-in
IN
register. LOW active.
Data enable signal to the built-in
IN
register. LOW active.
Area separation test pin.
Area separation test pin.
Clock signal input pin. Clock of
IN
16MHz is inputted.
IN
Zooming process data input pin.
IN
IN
Zooming process data input pin.
IN
IN
Zooming process data input pin.
IN
IN
Zooming process data input pin.
IN
Write enable signal to the line
memory. LOW active.
Read enable signal to the line
memory. LOW active.
10-clock behind signal of
RAMDATA0 ∼ 2.
Signal showing the effective image
area which is behind from AREA
signal by 5 clocks. LOW active.
Image data 1 line scanning start
IN
signal
Signal which shows the effective
image area. LOW active.
IN
(n+4)the line image data input pin.
IN
Signal which shows one page of
IN
image data. LOW active.
Advertisement
Table of Contents
