Sharp AR-5132 Service Manual page 34

Block diagram
∅ RS-EVEN
GND VDD
21 19 18
VOUT-EVEN 20 Output amplifier
GND 20
VGG 2
VOUT-ODD 3 Output amplifier
4 5
∅ RS-ODD
VDD
CCD GA pin index
Pin
Pin name
No.
1 NC
2 AD0
* *
Odd number pixel A/D conversion result
8 AD6
9 AD7 Odd number pixel A/D conversion result
11 BD0 Odd number pixel A/D conversion result
12 BD1
* *
Odd number pixel A/D conversion result
18 BD7
20 BD8 Sync signal from LSU (HSYNC)
Self running mode selection
21 SMODE
(in the shading correction)
22 WB Shading writing white/black control
23 SHINHB Shading effective signal
24 RESB Reset signal
In shading black writing, initialize at 0.
25 ADRSTB
Address reset black
28 WRCK Shading writing clock
30 32MCK 32MHz input
32 TST GA test pin
33 DACKE Even number D/A clock
34 DACK0 Odd number D/A clock
35 CCDCK Clock to be sent to the CCD PWB
φ ROG signal to be sent to the CCD PWB
36 ROGB
Sent to the CCD PWB to make φ LH signal valid.
37 SETB
Valid at 1.
38 CLMP Clamp signal
39 VRST Capacitor discharge signal
40 ADCK A/D clock
41 FWCK Write clock to the FIFO for image output
42 8MCK 8MHz clock
44 PXCK Image output pixel clock
45 RRESB Image output FIFO /RSTR (read reset)
46 RREB Image output FIFO /RE (read enable)
47 SRCK White correction data read clock
48 SRRESB White correction data FIFO /RSTR (read reset)
49 SRREB White correction data FIFO /RE (read enable)
50 SWCK White correction data FIFO WCK (write clock)
51 SH Line sync signal
53 ABD0
* *
Odd number/even number synthesized pixel signal
61 ABD7
63 BWCKE Black correction data write clock (even number)
64 BWCK0 Black correction data write clock (odd number)
∅ LH-EVEN ∅ 2-EVEN ∅ 1-EVEN
17 14 13
CCD analog shift register
Read out gate
Read out gate
CCD analog shift register
6 8 9 10 11
∅ LH-ODD ∅ 2-ODD ∅ 1-ODD
GND VDD
Function
[CCD GA and peripheral circuit]
The CCD control GA and the peripheral circuit are connected as
shown in the figure on the next page.
[CCD GA functions]
The CCD GA functions are classified as follows:
A. CCD reading
B. Shading correction data writing
The CCD reading is further classified as follows:
a. Supply of clocks and timing signals to the CCD PWB (which in-
cludes the CCD)
b. Supply of timing signals to the analog circuit which processes the
output signal from the CCD PWB
c. Supply of timing signals to the A/D convertor, the D/A convertor,
and the digital circuits.
12
∅ ROG
There are following kinds of digital circuit.
•
FIFO for shading (for white correction)
•
Latch for shading (for black correction)
•
FIFO for output of image data
d. Image data of the odd number channel and the even number
channel which are A/D converted are synthesized into one line.
The CCD reading operation is divided into the dependent running
mode and the self running mode by setting of the SMODE pin.
The dependent running mode is for copiers. Reading of one line is
performed at falling of the HSYNC signal from the LSU. Then the
machine enters the standby state for the next falling of the HSYNC
signal.
Therefore reading of one line is always synchronized with falling of
the HSYNC signal.
If the HSYNC interval falls below the specified level (326.5µs), the
HSYNC is dropped.
Since reading of one line is based on the counter operating at 8MHz
inside the GA, an error of max. 125ns is generated from falling of the
HSYNC to starting reading the one line.
When receiving image data through ICU, the SH which is outputted
from the CCD GA is used as the reference of timing.
In the self running mode, reading is started regardless of the SYNC
signal from outside when in shading correction.
Since reading of one line is started at the timing when the internal
counter becomes zero, the counter itself becomes zero when reset is
performed. Since the reset pin of the CCD control PWB is fixed to
HIGH, the timing for starting reading the line depends on the initial
state of the internal counter. The time (accumulated time, 334.38µs)
for one line is 2675 counts in 8MHz in the self running mode.
The accumulated time in the dependent running mode is 334.21µs
±0.1% (the LSU specification). In the self running mode, therefore,
the accumulated time is +0.05% of the standard value in the depend-
ent running mode.
In either mode of the self running and the dependent running, the SH
is used as the starting reference by the ICU, etc. The SH is turned
HIGH for one frequency of the timing clock PKCK for sending image
data from the CCD to the ICU.
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