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(2) RAM (AT28C64)
1
Outline
The RAM stores various setting data required for operations of the
AR-5132 system, causes of paper jams, and the counter data such
as trouble codes. (Batteries are not required.) Data transmission is
performed between the RAM and the main PWB immediately after
turning ON or OFF the power.
The AT28C64 is an EEPROM (Electrically Erasable ROM) of 8KByte
and operates on a single power source of 5V.
2
Features
Low power CMOS operating current max. 60mA
All memory write time: Average 0.625sec
5
RAM (IC115) pin signals
Pin No.
In/Out
1
—
2
IN
3
*
IN
10
11
*
IN/OUT
13
14
—
15
*
IN/OUT
19
20
IN
21
IN
22
IN
23
IN
24
IN
25
IN
26
IN
27
IN
28
—
Signal name
NC
A12
Address signal
A7
*
Address signal
A0
1/00
*
Data signal
1/02
GND
GND (0V)
1/03
*
Data signal
1/07
CS
RAM chip select signal. RAM is selected at LOW (0V).
A10
Address signal
RD
Read signal. RAM data are read into the CPU at LOW.
A11
Address signal
A9
Address signal
A8
Address signal
NC
WR
Write signal. Date are written into the RAM from the CPU at LOW (0V).
5V
Power source. @ medium index = (3) start/stop control circuit
9 – 11
3
Pin arrangement
PLASTIC
CERDIP
FLAT PACK
NC
1
A13
2
A7
3
A6
4
A5
5
A4
6
A3
7
AT28C64
A2
8
A1
9
A0
10
I/O0
11
I/O1
12
I/O2
13
VSS
14
4
Internal block diagram
X
BUFFERS
LATCHES
AND
DECODER
A0~A12
ADDRESS
INPUTS
Y
BUFFERS
LATCHES
AND
DECODER
CONTROL
C E
LOGIC
OE
AND
WE
TIMING
VCC
VSS
Function
28
VCC
WE
27
26
NC
A8
25
A9
24
A11
23
22
OE
21
A10
CE
20
I/O7
19
18
I/O6
17
I/O5
16
I/O4
15
I/O3
65.536-BIT
E²PROM
ARRAY
I/O BUFFERS
AND LATCHES
I/O0~I/O7
DATA INPUTS/OUTPUTS
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