Motorola MTP700 Detailed Service Manual page 53

TRANSCEIVER 400 MHz
RedCap2 (Microprocessor & DSP)
Figure 4.1-10 is a block diagram of the RedCap2 and its interfaces.
The RedCap2 RISC processor controls the operation of the transmitter, receiver, synthe-
sizer and audio (GCAP3) integrated circuits. It uses the Flash memory and SRAM, both
located externally.
RedCap2 employs SPI protocol (Serial Peripheral Interface) to communicate with the RF
ICs, display, keypad and other internal peripherals. The processor can be operated
through the RS232 interface by a personal computer to program the Flash memory with
firmware and codeplug.
Within the RedCap2 is the Digital Signal Processor (DSP) which performs modulation
and de-modulation functions for the radio. It also performs ACELP speech coding and
Forward Error Correction.
MTP700 Portable Radio / Detailed Service Manual
Encryption
Accelerator
DSP_IRQ
STDB
Baseband
CODEC
SRDB
Serial Port
SFSB(2)
BBP
Counter
SCKB(2)
STDA
Audio
SRDA
CODEC
Serial Port
SFSA(2)
SAP
DSP Timer
SCKA(2)
BRM
ADRS(22)
DATA(16)
R/W
OE
External
EB0,EB1 Inteface
Module
CS(6)
MOD
INT(6)
INT6/DSRA/
STDA/TRST
INT7/DTRA/SCLK/
SRDA/TMS
MOSIB
MISOB
QSPIB
QSCKB
SPICSB(5)
MOSIA
MISOA
QSPIA
QSCKA
SPICSA(5)
SIM
RST_OUT
Reset
RST_IN
Keypad
COLUMN(5)
Interface
ROW(5)
GPIO
COLUMN5/GPIO
ROW5/IC2B/GPIO
COLUMN6/OC1
COLUMN7/PWM
ROW6/DCDA/SC2A/DSP_DE
ROW7/RIA/ISCKA//TCK
Figure 4.1-10 RedCap2 - Block Diagram
PROM 2Kx24
DSP Peripheral
DMA
PRAM 40Kx24
YROM 0Kx16
YRAM 15Kx16
DSP
Core
XROM 0Kx16
Viterbi
Accelerator XRAM 12Kx16
Shared X/VIAC
MCU/DSP
RAM 2Kx16
Interface
MDI
Shared X/MCU
RAM 2Kx16
ROM 4Kx32
RAM 512x32
MCU
Core
PIG
Peripheral I/F
Gasket
GPReg
UARTA
MCU Timers/
PWM/PIT/
Watchdog
XYA(16)
XYRW,XYSEL,XYSTB
XYD(16)/TXA/RXA/GI
CKIH,CKIL
Clocks/PLL
CKOH,CKO
DEBUG(6)
MCU Debug
Layer 1
TOUT(16)
Timer
DSP_DE
JTAG(5)
JTAG/OnCE
MCU_DE
TEST
RTSB
CTSB
UARTB
TXB
RXB
MUX_CTL
RTSA/IC2A/
RESET_IN
M
CTSA/MCU_DE
U
X
TXA/TDO
RXA/IC1/TDI
4.1 - 19