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Philips Semiconductors
IC card interface
Table 1 Clock circuitry definition
MODE
HIGH
HIGH
HIGH
HIGH
HIGH
(2)
LOW
Notes
1. X = don't care.
2. In low-power mode.
3. f
= 32 kHz in low-power mode.
int
I/O circuitry
The three I/O transceivers are identical. The state is HIGH
for all I/O pins (i.e. I/O, I/OUC, AUX1, AUX1UC, AUX2 and
AUX2UC). Pin I/O is referenced to V
V
, thus ensuring proper operation in the event that
DD
V
V
.
CC
DD
The first side on which a falling edge is detected becomes
a master (input). An anti-latch circuitry first disables the
detection of the falling edge on the other side, which
becomes slave (output), see Fig.8.
After a delay time t
(between 50 and 400 ns), the logic 0
d
present on the master side is transferred on the slave side.
When the input is back to HIGH level, a current booster is
turned on during the delay t
both sides are back to their idle state, ready to detect the
next logic 0 on any side.
handbook, full pagewidth
I/O
I/OUC
1999 Oct 12
CLKSEL
CLKDIV1
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
X
(1)
X
X
and pin I/OUC to
CC
on the output side and then
d
t d
Fig.8 Master and slave signals.
CLKDIV2
LOW
LOW
HIGH
HIGH
(1)
(1)
X
(1)
(1)
X
In the event of a conflict, both lines may remain LOW until
the software enables the lines to be HIGH. The anti-latch
circuitry ensures that the lines do not remain LOW if both
sides return HIGH, regardless of the prior conditions.
The maximum frequency on the lines is approximately
200 kHz.
When CS is HIGH, I/OUC, AUX1UC and AUX2UC are
internally pulled-up to V
CS is LOW, I/OUC, AUX1UC and AUX2UC are
permanently HIGH (with integrated 100 k pull-up
resistors connected to V
t d
10
FREQUENCY OF
CLK
1
f
2
int
1
f
4
xtal
1
f
2
xtal
STOP low
STROBE
STOP low
with 20 k resistors. When
DD
).
DD
t d
conflict
idle
MGD703
Product specification
TDA8002C
FREQUENCY OF
CLKOUT
1
f
2
int
f
xtal
f
xtal
f
xtal
f
xtal
1
(3)
f
2
int
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