Integra DHC-40.1 (B) Service Manual page 22

A B
SCHEMATIC DIAGRAM-16
U005
SPI0 & control signals
1
from1stDSP
to 2nd DSP
2
3
4
+2.4VDSP
GND_ARM
5
VDD_DSP3.3V
+5VHD
DSP3_CLKIN
C
HDMI CIRCUIT PC BOARD BAHDM-0132-1E (-8)
(PART-21) DSP 2ND Section
Mid High
R3411 220 2.2K
R3410
330 470
R3416
+3.3V
R3415 NC
330
DIGSDO R3416
47
DIGSDI R3418
C3410 105Z
47
ADSP2_SD0 R3420
47
ADSP2_SD1 R3423
47
ADSP2_SD2 R3424
47
ADSP2_SD3 R3425
R3427 47
ADSP2_SD4
47
ADSP2_SD5 R3428
33X4
EM2_A12
C3417 105Z
EM2_A13
EM2_A14
C3419 105Z
EM2_A15
R3429
C3421 105Z
Val
RSVD1 R3434
TP106
R3436 330
ADSP1_SD0
C3426 105Z
330
ADSP1_SD1 R3437
330
ADSP1_SD2 R3438
C3428 105Z
330
ADSP1_SD3 R3440
R3441 330
ADSP1_SD4
330
ADSP1_BCK R3442
330
ADSP1_LRCK R3443
ADSP2_BCK MMZ1608Y601B
L3403
R3444 330 R3446 47
47
ADSP2_LRCK R3447
ADSP_MCK
C3442 106K/6.3
DSP2_RST
106K/6.3
C3448
Q3404
BD7820
C3449 105Z
C3451 105Z
R3466 3.9KF
VDD_D2COR1.2V
22KF
R3465
+3.3V
BLM18PG121SN1D
220KF
1 2 R3467
L3409
D3401
1SS352
Q3406
TA48033BF
1 3 VDD_DSP3.3V
I O
GND_ARM
D E
+1.2V
109
110
111
112
113
AXR0[0] VSS
114
VSS SPIO_SIMO
115
AXR0[1] SPIO_SOMI/I2C0_SDA
116
AXR0[2] DVDD
117
AXR0[3]
118
VSS
119
AXR0[4]
120
AXR0[5]/SPI1_SCS
Q3402
121
AXR0[6]/SPI1_ENA]
TMS320DA708
122
AXR0[7]/SPI1_CLK
123
CVDD
D788E001BRFP266
124
VSS
125
DVDD
126
AXR0[8]/AXR1[5]/SPI1_SOMI
127
AXR0[9]/AXR1[4]/SPI1_SIMO
128
CVDD
129
THERMALPAD
VSS
130
AXR0[10]/AXR1[3]
131
AXR0[11]/AXR1[2]
132
CVDD
133
VSS
134
AXR0[12]/AXR1[1]
135
AXR0[13]/AXR1[0]
136
DVDD
137
AXR0[14]/AXR2[1]
138
AXR0[15]/AXR2[0]
139
ACLKR0
140
VSS
141
AFSR0
142
ACLKX0
143
AHCLKR0/AHCLKR1
144
AFSX0
R3448 47
C3443 105Z
R3464
106K/6.3
C3446
1K
NC_ACF451832-333
L3404
BLM18PG121SN1D
L3408
Q3405
TC7WU04FU
1 8
VD MMZ1608Y601B
2 7 L3410
390
3 6 R3470
MMZ1608Y601B
4 5
L3411
GND
R3471 390
R3472 1M
X3401
17.734MHz
F G
EM2_A14
EM2_A13
EM2_A12
EM2_A11
EM2_A10
EM2_A9
EM2_A8
72 EM2_A7
VSS
71 R3417 EM2_CKE EM2_A18
EM_CKE
33
70 L3401 R3419 EM2_CLK EM2_A19 TP110
EM_CLK
0 75 C3411
69 EM2_WE
VSS
68 C3412 #100D DSP2_RST
DVDD
105Z R3422 R3421 1K
67 EM2_UDQM
EM_WE_DQM[1]
33
66
C3414 102J
EM_D[8]
R3426
65 C3415 EM2_D8
CVDD TP111
64 105Z EM2_D9 EM2_A17
EM_D[9]
63 EM2_D10 EM2_A16
EM_D[10]
62 EM2_D11 EM2_A6
VSS
61 EM2_A5
33X4
EM_D[11]
C3416
60 EM2_A4
DVDD
59 105Z EM2_A3
EM_D[12]
R3430
58 EM2_D12 EM2_A2
EM_D[13]
C3418
57 EM2_D13 EM2_A1
CVDD
56 105Z EM2_D14 EM2_A0
EM_D[14]
55 EM2_D15
EM_D[15]
54
33X4
VSS
53 C3422 GND_ARM
CVDD
R3435
52 105Z EM2_D0
EM_D[0]
51 EM2_D1
EM_D[1]
C3424 C3425
50
DVDD
49 105Z EM2_D2 EM2_D0 105Z
EM_D[2]
C3427
48 33X4
EM_D[3]
R3439
47 EM2_D3 EM2_D1 105Z
VSS
46 EM2_D4 EM2_D2
EM_D[4]
45 EM2_D5
EM_D[5]
44 C3430 EM2_D6 EM2_D3
CVDD
105Z
43 33X4 EM2_D4
EM_D[6]
42 C3431 C3432
DVDD
41 105Z EM2_D5 105Z 10
EM_D[7]
R3445
40 EM2_D7 EM2_D6 11
VSS
39 EM2_LDQM 12
EM_WE_DQM[0]
38 EM2_WE EM2_D7 13
EM_WE
37 EM2_CAS C3434 14
EM_CAS
105Z
33X4 EM2_LDQM 15
EM2_WE 16
EM2_CAS 17
EM2_RAS 18
+1.2V
EM2_SDCS 19
EM2_BA0 20
+3.3V
EM2_BA1 21
EM2_A10 22
EM2_A0 23
EM2_A1 24
EM2_A2 25
EM2_A3 26
C3445
27
105Z
106K/6.3
C3447
C3450
105Z
+3.3V
DHC-40.1
H
GND_ARM
1 48 EM2_A15
A15 A16
2 47
A14 BYTE
3 46
A13 GND
4 45 EM2_D15
A12 Q15/A-1
5 44 EM2_D7
A11 Q7
6 43 EM2_D14
A10 Q14
7 42 EM2_D6
A9 Q6
8 41 EM2_D13
A8 Q13
9 40 EM2_D5
A19 Q5
10 39 EM2_D12
A20 Q12
11 38 EM2_D4
WE Q4
12 37 C3413
RESET VCC
105Z
13 36 EM2_D11
NC Q11
14 35 EM2_D3
WP/ACC Q3
15 34 EM2_D10
RY/BY Q10
16 33 EM2_D2
A18 Q2
17 32 EM2_D9
A17 Q9
18 31 EM2_D1
A7 Q1
19 30 EM2_D8
A6 Q8
20 29 EM2_D0
A5 Q0
21 28 EM2_OE
A4 OE
22 27
A3 GND
23 26 EM2_FCS
A2 CE
24 25 EM2_BA1
A1 A0
106K/6.3
VDD_2FLS3.3V C3420
L3402 C3423
BLM18PG121SN1D
105Z
+3.3V
1 54
VDD VSS
2 53 EM2_D15
DQ0 DQ15
3 52
VDDQ VSSQ
4 51 EM2_D14
DQ1 DQ14
5 50 EM2_D13
DQ2 DQ13
C3429
6 49
VSSQ VDDQ
7 48 105Z EM2_D12
DQ3 DQ12
8 47 EM2_D11
DQ4 DQ11
9 46
VDDQ VSSQ
45 EM2_D10
DQ5 DQ10
44 EM2_D9
DQ6 DQ9
43 C3433
VSSQ VDDQ
105Z
42 EM2_D8
DQ7 DQ8
41
VDD VSS
40
LDQM NC
39 EM2_UDQM
WE UDQM
38 EM2_CLK
CAS CLK
37 EM2_CKE
RAS CKE
36
CS NC
35 EM2_A11
BA0 A11
34 EM2_A9
BA1 A9
33 EM2_A8
A10 A8
32 EM2_A7
A0 A7
31 EM2_A6
A1 A6
30 EM2_A5
A2 A5
29 EM2_A4
A3 A4
28
VDD VSS
VDD_2SDR3.3V