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M Z 3500
8 2 5 1
8 2 5 1
Chip address[0001/xxxx]
I N
U i x
OUT)
CLK
DSK
DTK
CTS
RTS
TXI)
TXRDY
TXE
TXC
RXD
RXRDY
RXC
SYN/BD
I N
I N
OUT
! N
OUT
OUT
N.C.
N.C.
I N
I N
OUT
I N
N.C.
2.45MHz Clock
DATA SETREADY
DATA TERMINAL READY
CLEAR TOSEND
REQUEST TOSEND
TRANSMITTER DATA
TRANSMITTER CLOCK
RECEIVE DATA
RECEIVER READY
RECEIVE CLOCK
READY
CS
PO (MPER SUT), ER
CD
RD
OUT 0 of 8253
SD
To siib-CPU of
8253 OUT
8 2 5 3
8 2 5 3
Chip address[0010/xxxx]
I N
* U X H
O U T f l
2 X
"
C L K O
GATEO
OUTO
CLK1
GATE1
OUT1
CLK2
GATE2
OUT2
IN
I N
OUT
I N
I N
OUT
I N
IN
OUT
2.45MHZ
Vcc
To TXC, RXC of the 8251
2.45MHZ
From OUT2
MUSIC
2.45MHZ
Vcc
To GATE 1
INTO TO MAIN FROM SUB
c
POWER ON RESET
S O O - S I W ( I O R Q - W R
O
f SUB)
1 N T R = L ( F R O M M A I N )
INTO
H
L
H
INT TO SUB FROM KEY
STK= ( L )
- 77 -
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