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MZ 3500
6-6. 8253 Controls
Baud rate of this interface will be determined by the clock
Output of the 8253. The 8251 is configured such that its
baud rate is 1/16 of the input clock and has the following
relation between the 8253 Output clock and the baud rate:
8253 input frequency: 2457.6kHz
8253 Mode set: Mode 3(rectangle waveform rate generator)
Control Signals
Baud rate
1 1 0 ,f -
3 0 0
6 0 0
1 2 0 0
24 00
4 8 0 0
9 6 0 0
8 2 5 3
Output frequency
I 7 6 0
H z
4 8 0 0
9 6 0 0
1 9 2 0 0
3 8 4 0 0
7 6 8 0 0
1 5 3 6 0 0
8 2 5 3
Parameter
1 3 9 6.3 6
5 1 2
256
1 2 8
6 4
32
1 6
Signal name
Transmission enabled
Data set ready
Carrier detect
Ready
Equipment ready
Paper out
Symbol
CS
DR
CD
READY
ER
PO
IN/OUT
-* Peripheral
-* Peripheral
— Peripheral
— Peripheral
«- Peripheral
*- Peripheral
Function
When high, data input from a peripheral is enabled.
When Iow, data input from a peripheral is disabled.
Goes high when power is on to the interface unit.
(SW6-ON) High at all times when power is on to the interface unit.
(SW6-OFF) Goes high only when data is on Output.
Data Output from the interface is enabled.
(ON) Data is Output from the interface.
(OFF) Waits for data Output.
NOTE: A maximum of two bytes are Output after the signal goes from high to Iow
state.
Indicates that the peripheral is ready. It results in an error if Iow or open when data
is sent from the interface. This signal will be invalidated when the SW5 is turned
off.
(SW7-ON) Causes an error if set high during data Output.
(SW7-OFF) Causes an error if set Iow during data Output.
6-7. Description of LSI's
1) UPD8251AC (Programmable Communication Interface)
The UPD8251A is a USART (Universal Synchronous/
Asynchronous Receiver/Transmitter that was specifical-
ly designed for data communication.
The USART receives parallel data from the CPU and
converts it into Serial data before transmitting. Also,
serial data is received from an external Circuit and trans-
ferred to the CPU after converting it into parallel. The
CPU can monitor the current state of the USART at
any time (data transfer error, and control signal of
, SYNDETandTXEMPTY.
, eatures
• 8080A/8085A compatible
• Synchronous/asychronous Operation
• Synchronous Operation
5 — 8 bits Character
Clock rate: baud rate x 1, x16, x64
BREAK Character generation
Stop bit: 1, 1.5. 2 bits
Error Start bit detection
Automatic break detection and Operation.
• Baud rate: DC - 64K baud
• Full-duplex
Double buffer type transmitter/receiver
• Error detect
Parity, overrun, framing
• Input/output TTL compatible
• N-channel MOS
• Single +5V supply
• Single phase TTL level clock
• 28-pin, plastic DIP
•
Intel 8251A compatible
Pin configuration (Top View)
«
27
K)DO
7-0 VCC
O«
25
-ORXC
o
25
»ORTS
D«
22
ODSR"
RESET
CLK
TXD
—'-2—&OTXEMPTY
CTS
SYNDET BD
TXRDY
Block diagram
D7-DOO4— ^-»
RESET 0 — — »•
WKO
M:
Data
bus
buffer
Read/
write
control
logic
5
D S K o
X
rr^o^HK:
K T S 0 4
CJ
MODEM
Controller
8
8
^_
8
8
8
8
-»
1
Transmissio
buffer '
( P-»S )
t 4
Transmissic
control '
Reception
buffer
( S-+P
)
t 1
Receiver
control
n
KJTXD
1
K5TXRDV
K)TXE
x — OTXC
NDKXKi)V
«
»OSYNDKT BI)
Internal da
- 75 -
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