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M Z 3500
3-2. Main CPU and I/O port
M
A
I
N
C
P
U
[NO
Ix
A2
A3
A4
A5 i
A6
"A
V\ r
A7
P
C
IORQ
MT
A
YO
Y 1
Oi A
Y3
Y4
G2 B
Y5
Gl
Y6
74LS138
This paragra
Connector
Port select an
1 FC2
The address
_
\~f\
~~\
is decoded it
v
select signal.
T
f^i -,-,.,-
Table below
^
v# ."> r L)C
signal functic
J
V
J
0 MFÜC
0
T"O IOMF
L
|
3
U IOABCMEMORY
MAPPER)
ADDRESS
A7 A6
A5 A4 A3 A2 A1 AO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
0
0
0
X
X
t
'
\
-
\
O
Q
1
X
X
^
t
'
\
O
t
O
X
X
1
1
1
0
1
1
X
X
1
1
1
1
Q
O
X
X
1
1
1
1
0
1
X
X
1
1
1
1
1
0
X
X
1
1
1
1
1
1
X
X
HEX
00
01
DE
DF
E O
E3
E4
E 7
E8
E B
E C
EF
F O
F 3
F 4
F 7
F 8
F B
FC
F F
NOT USE
NOT USE
SFDC (UPD765)
IOSF
INTR
NOT USE
MFDC (UPD765)
IOMF
IOAB (MEMORY MAPPER)
SPD interface FDC chip select.
AO used for RD and WR.
A1 is "don' t care".
SPD interface I/O port and DMAC chip select.
!
Interrupt signal from the sub-CPU to the main CPU.
i
Flipflop resetting signal.
MFD interface FDC chip select.
MFD interface I/O port.
AO used for RD and WR.
AI is "don't care".
I/O port select in the memory mapper
AOand A1 used during RD, WR.
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