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M/-3500
CH48 -
0: For 40 digil display
Relation bctween V R A M address and screen
1 : For 80 digit display
There is a 40/80 digit switching signal I/O port
in the gate array of CSP1 and CSP2, bul, the I/O
signal calied CH48 is provided apart from the I/O
port.
l 08/16 -
I/O port inside CSP1 and CSP2.
7) Graphic V-RAM Address
Relation between V R A M address and screen (640 x 200 dots)
8-bit s t r u c t u r e
t
m
,
m
,
Graphic
address
map for
200 rasters
L-OO
l IV U-
0000
0001
0002
0003
0050
0051
OOAO
OOKO
3F30
00 >tl-
D09I-'
31" K
16-bit structure
Graphic
address
map for
400 rasters
CRTC block diagram
Color graphic VRAM PWB (opnnn)
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