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M 7. 3500
4.-5. Master slice LSI (CSP-1) SP6102C-002 signal description
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2
3
4 - 6
7 - 9
10
11
12
13
14
15
16-18
19
20.21
22
23
24
25
26-28
29
30
31
32
33
34
35
36
37
38
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40
Prlorily
Signal Name
HSYi
NABC
CSR
ASO ~ AS2
DSO - DS2
G2
NWRO
NVB
NVR
NVB
FYD2
AT2 ~ AT4
CH
GND
DSP2
VID2
LCO
AT1
LC1 ~ LC3
NCL4
HSYO
RA40
VIDI
B1
R1
Öf
SU
82
R2
BLNK
Vcc
IN/OUT
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
IN
Horizontal synchronizing signal from the GDC1 . Also, it becomes the refresh timing signal in the
dynamic RAM mode.
Input from the UPD7220 GDC1 . When the GDC1 is in the Character display mode, the attribute,
blinking timing and line counter clear Signals are muttiplexed.
Input from the GDC1 which is the Cursor display input when the GDC1 is in the Character display
mode.
Address bus input from the sub-CPU.
ABO = ASO, ABI = AS1 , AB2 = AS2
Data bus input from the sub-CPU.
DBO = DBO, DB1 = DB1, DB2 = DB2
Green image Output to the CRT2.
CSP1 I/O port Select Signal (OUT # 5 X )
Input of the blue image from the graphic R A M ( A ) and (B).
Input of the red image from the graphic RAM (B), (C), and (D).
Input of the green image from the graphic RAM (E) and (F).
Input of the graphic RAM parallel/serial conversion IC 74LS166 shift out Clock.
(Used to latch the image data in CSP1.)
Attribute data input from the 21 14A-1 attribute RAM.
f AT-2 - Horizontal line/R ]
AT-3 - Reverse/G
[AT-4 - Blink
J
Input of Character display data signal.
0V supply
Input of display timing signal supplied from the CSP-2. (BLINK signal from the GDC2 is delayed by
two flipflop intervals in the CSP-2 to creat this signal.)
VIDEO Output to CRT2.
Character CG line counter Output.
(Becomes address input to the CG when LCO = CG address AO.)
Attribute data input (Vertical line/B) from the 2114A-1 attribute RAM.
Character CG line counter Output.
(LC1 - AI, LC2 = A2, LC3 = A3CG = A3)
Character CG Output data latch timing.
CRT1, 2 horizontal synchronizing signal.
The Signal that turns high level when the 400-raster CRT is in connection. LDA, 01 H OUT*56
VIDEO Output to the CRT1.
Blue image output to the CRT1 .
Red image output to the CRT1.
Green image Output to the CRT1 .
Character CG Output parallel/serial Converter IC 74LS166 shift load signal, and Character CG address
latch signal input. (Used for the image data latch signal in the CSP-1 and horizontal synchronizing
signal delay flipflop Clock.)
Blue image Output to CRT2.
Red image output to CRT2.
Erase signal from the GDC1 which becomes input at the following times.
1. Horizontal flyback period
2. Vertical flyback period
3. Period from the execution of the SYNC SET command to the execution of the DISP START
command.
4. Line drawing period
+5V supply.
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