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M Z 3500
46. LSI (CSP-2) SP6012C-003 Signal Description
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Polarity
Signal Name
HSY2
BLK2
DWE
AD14-AD15
DBI2
DBI1
BUSG
SO E
SWE
0816
RAS1
RAS2
AS3
NWRO
DSO-DS1
RA40
M40
GND
SL2
RASA
2CM2
LOAD
Vcc
FYD2
2CK1
SL1
SL1
CGOE
DB1C-DB1A
R A S - C -
RAS-B
IN/OUT
IN
IN
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Horizontal synchronizing Signal from GDC2 which also becomes the refresh tirniny .ijnai in the
dynamic RAM mode.
Erase Signal input from the GDC2 which is supplied 4T the following times:
1. Horizotal flyback period.
2. Vertical flyback period.
3. Period from the execution of the SYNC SETcommand to *t*e execution of the D ISP START
command.
4. Line drawing period.
WRITE ENABLE Output for the graphic dynamic RAM.
Input of the display Output Signals (AD14, AD1 5) from GDC2.
(Used to create DBIA-DBTC in the CSP-2.)
Input from the GDC2 by which the image memory Output is sent on the data bus.
(Usedto create RASA-RASC, CAS. PS, DWE in the CSP-2.)
Input from the GDC1 by which the image memory Output is sent on the data bus.
(Used to create BUSG. SOE. SWE in the CSP-2.)
Gate Signal of the bidirection bus buffer (LS245) which is used to read/write attnbute. and Character.
data from the static RAM (21 14A-1 . 61 16P-3).
OUTPUT ENABLE for Character static RAM (61 16P-3).
WRITE ENABLE for attribute, Character static RAM.
8-bit/word and 16-bit/word select Signal.
(8-bit/word chosen with LDA. OOH OUT#5D, and 16-bit/word is chosen with LDA, 01 H OUTiSD.)
Memory control Signal RAS from GDC1.
(Used to create CGOE. SL1 in CSP-2.)
Memory control Signal RAS from CDC3.
(Used to create SL2. LOAD, RASA-RASC. CAS. FS. DBIA-DBIC, DSP2 in CSP-2.)
Address bus input from the sub-CPU (ASS = AB3)
Chip select (OUT#5X) of the I/O port in CSP-2.
Data bus input from the sub-CPU (DSO = DBO, DS1 = DB1 ).
The Signal that goes to high level (input from CSP-1 ) when the 400-raster CRT is connected.
(Used for Clock frequency selection in CSP-2.)
Clock input from the Clock generator (39.32MHz, for 400-raster mode.)
0V supply
Graphic DRAM Output parallel/serial Converter IC 74LS166 shift load signal.
Graphic DRAM (A). (B) RAS Signal.
Double Character Clock Output. In the Character display mode, a single phase Clock of the half the
one Character wide frequency is supplied. In the graphic display mode, a single phase clock of
8/16 dot frequency is supplied to GDC2.
Graphic DRAM Output parallel/serial Converter IC 74LS166 ioad timing clock.
+5V supply.
Graphic DRAM Output parallel/serial Converter IC 74LS166 shift out clock.
Double Character Clock Output same äs 2CK2. In the Character display mode, a single phase clock
of one half the one Character wide frequency is supplied to GDC1 .
Character CG Output parallel/serial Converter IC 74LS166 shift out clock.
Character CG Output parallel/serial Converter IC LS166 shift load signal.
Character CG address.
Character CG Output enable signal.
Timing signal by which the graphic DRAM Output is sent on the data bus.
Graphic DRAM RAS (ROW ADDRESS SELECT) signal
RAS-B; RAM(C), (D)
RAS-C; RAM (E), (F)
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