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M Z 3500
MAIN CPU
I/O PORT IN MEMORY MAPPER
ADDRESS
A7|A6|A5|A4|A3|A2|Al|AO
1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1
II EX
U f~
KI)
FE
FF
UHUS
Dl
00
D7
ül
DO
1)7
D6
D5
D4
D2
Dl
DO
D4
D3
D2
Dl
DO
D7
D6
D5
1)4
D3
D2
Dl
DO
D7
D6
I / O
OUT
IN
IN
SKQH
i-; i
S K K S
M S I
MSO
M A3
MA2
M A I
M A O
MO2
MOI
MÜO
S\\'4
swg
SW2
swi
SHC
FD 3
FD2
FD1
SKDY
SACK
INP2
INT1
I N F O
ME2
M El
-•->
SRQ: Bus request Irom the main CPU to the sub-CPU.
7-V
Sub-CPU reset signal
Memory System define
Bank select signal to memory area of COOO-FFFF.
,J
•A
Bank select Signal to memory area of 2000-3FFF.
System assign switch
FD assign
(SW8)
•fr
Sub-CPU READY signal
•fr
Sub-CPU acknowledge signal
Interrupt Status
.1. All Output Signals are reset to Iow level upon power on,
l
except for SRBQ that goes high.
2. Noted with a star mark "6" are Input/Output Signals, and
rest of others are processed in the LSI.
#1 I/O port Output of ME1 and ME2 uses the memory at
the addresses.
ME2->8000~BFFF
ME1->-4000~7FFF
When ME1 and ME2 are in high state, RSAB (RASA) is
inhibited during memory addresses in RAM-A that
correspond to overlayed addresses for ME1 and ME2.
This is not true during SD1 mode.
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TO Vf
Wait timing generator
WAIT is issued once per main CPU fetch cycle.
Its outut is tri-state.
- L>3 -
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