Clarion MAX668RVD Service Manual page 40

pin 10: A out R+ : O : Audio signal right channel positive output.
pin 11: A out L- : O : Audio signal left channel negative output.
pin 12: A out L+ : O : Audio signal left channel positive output.
pin 13: VSS : - : Negative supply voltage.
pin 14: VDD : - : Positive supply voltage.
pin 15: DZF R : O : Zero detection flag output.
pin 16: DZF L : O : Zero detection flag output.
658-0246-03 C0JBAA000372
1
2
GND 3
658-0246-05 C0CBADC00084
GROUND
658-0246-06 C0JBAA000356
1
2
GND 3
658-0246-07 MN13821JP
OUT 1
VSS 3
658-0246-09 C3ABPJ000074
Terminal Description
pin 1: VDD : - : Positive supply voltage.
pin 2: D 0 :I/O: Data input/output.
pin 3: VDD : - : Positive supply voltage.
pin 4: D 1 :I/O: Data input/output.
pin 5: D 2 :I/O: Data input/output.
pin 6: VSS : - : Negative supply voltage.
pin 7: D 3 :I/O: Data input/output.
pin 8: D 4 :I/O: Data input/output.
pin 9: VDD : - : Positive supply voltage.
pin 10: D 5 :I/O: Data input/output.
pin 11: D 6 :I/O: Data input/output.
pin 12: VSS : - : Negative supply voltage.
pin 13: D 7 :I/O: Data input/output.
pin 14: NU : - : Not in use.
pin 15: VDD : - : Positive supply voltage.
pin 16: DQM 0 : IN : When DQM is sampled HIGH, input data
is masked during a WRITE cycle, and the
929-2506-00
Single 2-inputs AND GATE
(TC7SET08FU)
5 VDD
4
Positive Voltage Regurator 5.0V
(uPC78L05T)
3 INPUT
2 GROUND
1 OUTPUT
Single 2-inputs AND GATE
(TC7SH08FU)
5 VDD
4
Voltage-down detection IC
(Nch open drain output)
2 VDD
64Mb x 32 SDRAM
(MT48LC2M32B2P-7IT)
pin 17: WE : IN : Write enable signal input.
pin 18: CAS : IN : Column address strobe input.
pin 19: RAS : IN : Raw address strobe input.
pin 20: CS : IN : The chip select command input.
pin 21: NU : - : Not in use.
pin 22: BA 0 : IN : Bank address input.
pin 23: BA 1 : IN : Bank address input.
pin 24: A 10 : IN : Address signal input.
pin 25: A 0 : IN : Address signal input.
pin 26: A 1 : IN : Address signal input.
pin 27: A 2 : IN : Address signal input.
pin 28: DQM 2 : IN : When DQM is sampled HIGH, input data
pin 29: VDD : - : Positive supply voltage.
pin 30: NU : - : Not in use.
pin 31: D 16 :I/O: Data input/output.
pin 32: VSS : - : Negative supply voltage.
pin 33: D 17 :I/O: Data input/output.
pin 34: D 18 :I/O: Data input/output.
pin 35: VDD : - : Positive supply voltage.
pin 36: D 19 :I/O: Data input/output.
pin 37: D 20 :I/O: Data input/output.
pin 38: VSS : - : Negative supply voltage.
pin 39: D 21 :I/O: Data input/output.
pin 40: D 22 :I/O: Data input/output.
pin 41: VDD : - : Positive supply voltage.
pin 42: D 23 :I/O: Data input/output.
pin 43: VDD : - : Positive supply voltage.
pin 44: VSS : - : Negative supply voltage.
pin 45: D 24 :I/O: Data input/output.
pin 46: VSS : - : Negative supply voltage.
pin 47: D 25 :I/O: Data input/output.
pin 48: D 26 :I/O: Data input/output.
pin 49: VDD : - : Positive supply voltage.
pin 50: D 27 :I/O: Data input/output.
pin 51: D 28 :I/O: Data input/output.
pin 52: VSS : - : Negative supply voltage.
pin 53: D 29 :I/O: Data input/output.
pin 54: D 30 :I/O: Data input/output.
pin 55: VDD : - : Positive supply voltage.
pin 56: D 31 :I/O: Data input/output.
pin 57: NU : - : Not in use.
pin 58: VSS : - : Negative supply voltage.
pin 59: DQM 3 : IN : When DQM is sampled HIGH, input data
pin 60: A 3 : IN : Address signal input.
pin 61: A 4 : IN : Address signal input.
pin 62: A 5 : IN : Address signal input.
pin 63: A 6 : IN : Address signal input.
pin 64: A 7 : IN : Address signal input.
pin 65: A 8 : IN : Address signal input.
pin 66: A 9 : IN : Address signal input.
pin 67: CKE : IN : Clock enable signal input.
pin 68: CLK : IN : The clock pulse input.
pin 69: NU : - : Not in use.
pin 70: NU : - : Not in use.
pin 71: DQM 1 : IN : When DQM is sampled HIGH, input data
pin 72: VSS : - : Negative supply voltage.
pin 73: NU : - : Not in use.
- M2 -
output buffers are placed in a High-Z state
during a READ cycle. DQM 0 corresponds
to D0-D7.
is masked during a WRITE cycle, and the
output buffers are placed in a High-Z state
during a READ cycle. DQM 1 corre-
sponds to D8-D15.
is masked during a WRITE cycle, and the
output buffers are placed in a High-Z state
during a READ cycle. DQM 2 corresponds
to D16-D23.
is masked during a WRITE cycle, and the
output buffers are placed in a High-Z state
during a READ cycle. DQM 3 corre-
sponds to D24-D31.