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• IC Pin Function Description
MAIN BOARD IC506 CXD9862R (DIGITAL AUDIO PROCESSOR)
Pin No.
Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCKOUT
15
16
17
18
19
TE
L 13942296513
20
21
22
23 to 25
SDO1 to SDO3
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
www
43
44
45
.
46
47
48
http://www.xiaoyu163.com
I/O
VSS
—
Ground terminal
XRST
I
System reset signal input from the system controller "L": reset
EXTIN
I
Master clock signal input terminal (not used)
LRCKI3
I
L/R sampling clock signal input terminal (not used)
VDDI
—
Power supply terminal (+2.5V)
BCKI3
I
Bit clock signal input terminal (not used)
PLOCK
O
Internal PLL lock signal output terminal (not used)
VSS
—
Ground terminal
MCLK1
I
System clock input terminal (13.9 MHz)
VDDI
—
Power supply terminal (+2.5V)
VSS
—
Ground terminal
MCLK2
O
System clock output terminal (13.9 MHz)
Master/slave setting terminal "L": internal clock, "H": external clock
MS
I
(fixed at "L" in this set)
O
Internal system clock output to the stream processor
LRCKI1
I
L/R sampling clock signal input from the digital audio interface
VDDE
—
Power supply terminal (+3.3V)
BCKI1
I
Bit clock signal input from the digital audio interface
SDI1
I
Audio serial data input from the digtal audio interface
LRCKO
O
L/R sampling clock signal output to the stream processor
BCKO
O
Bit clock signal output to the stream processor
VSS
—
Ground terminal
KFSIO
I
Audio clock signal input from DSP
O
Audio serial data output to the stream processor
SDO4
O
Audio serial data output terminal (not used)
SPDIF
O
SPDIF signal output terminal (not used)
LRCKI2
I
L/R sampling clock signal input from DSP
BCKI2
I
Bit clock signal input from DSP
SDI2
I
Audio serial data input from the digital audio interface
VSS
—
Ground terminal
HACN
O
Acknowledge signal output to the system controller
HDIN
I
Serial data input from the system controller
HCLK
I
Serial data transfer clock signal input from the system controller
HDOUT
O
Serial data output to the system controller
HCS
I
Chip select input from the system controller
GP12
I
Write signal input from the system controller
GP13
O
SD-RAM chip enable output terminal (not used)
GP14
O
Row address strobe signal output terminal (not used)
VDDI
—
Power supply terminal (+2.5V)
VSS
—
Ground terminal
GP15
O
Column address strobe signal output terminal (not used)
OE0
O
Output terminal of data output mask (not used)
CS0
O
Chip select signal output to the S-RAM
x
ao
y
WE0
O
Write enable signal output to the S-RAM
i
VDDE
—
Power supply terminal (+3.3V)
WMD1
I
External memory wait mode setting terminal (fixed at "H" in this set)
VSS
—
Ground terminal
http://www.xiaoyu163.com
8
Q Q
3
6 7
1 3
u163
.
HCD-FX888K
2 9
9 4
2 8
Description
1 5
0 5
8
2 9
9 4
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9 9
2 8
9 9
61
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