Multicast Traffic; Route Processor Functions - Cisco ASR 9000 series Reference Manual

Route Switch Processor Card

Multicast Traffic

Multicast traffic is replicated in the switch fabric. For multicast (including unicast floods), the
Cisco ASR 9000 Series replicates the packet as necessary at the divergence points inside the system, so
that the multicast packets can replicate efficiently without having to burden any particular path with
multiple copies of the same packet.
The switch fabric has the capability to replicate multicast packets to downlink egress ports. In addition,
the line cards have the capability to put multiple copies inside different tunnels or attachment circuits in
a single port.
There are 64K Fabric Multicast Groups in the system, which allow the replication to go only to the
downlink paths that need them, without sending all multicast traffic to every packet processor. Each
multicast group in the system can be configured as to which line card and which packet processor on that
card a packet will be replicated to. Multicast is not arbitrated by the VOQ mechanism, but it is subject
to arbitration at congestion points within the switch fabric.

Route Processor Functions

The Route Processor (RP) performs the ordinary chassis management functions. The
Cisco ASR 9000 Series runs Cisco IOS XR software, so the RP runs the centralized portions of the
software for chassis control and management.
Secondary functions of the RP include boot media, Building Integrated Timing Supply (BITS) timing,
precision clock synchronization, backplane Ethernet communication, and power control (through a
separate CAN bus controller network).
A key function of the RP is to be able to communicate with line cards and the other RSP card in the
chassis through the switch fabric.
Figure 2-5
Figure 2-5
System
Timing
Cisco ASR 9000 Aggregation Services Router Overview and Reference Guide
2-10
D R A F T — C I S C O C O N F I D E N T I A L
shows the route processor interconnections.
Route Processor Interconnections
CPU
GE
Switch
RSP
CPU
Interface
FPGA
Packet
VOQ
Diversion
Scheduler
FPGA
Fabric
Interface
Chip
Fabric
Chip
Chapter 2 Functional Description
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